參數(shù)資料
型號： XRT83L34
廠商： Exar Corporation
英文描述： QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： 四T1/E1/J1收發(fā)左/上海收發(fā)器和時鐘恢復(fù)和抖動衰減器
文件頁數(shù)： 6/82頁
文件大?。?/td> 447K
代理商： XRT83L34
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
II
Figure 13. Simplified Diagram for the Internal Receive and Transmit Termination Mode ........ 29
T
ABLE
7: R
ECEIVE
T
ERMINATIONS
....................................................................................................... 30
Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ............. 30
TRANSMITTER (C
HANNELS
0 - 3) ............................................................................................................ 31
Transmit Termination Mode ...................................................................................................................... 31
External Transmit Termination Mode ........................................................................................................ 31
Figure 15. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ................... 31
T
ABLE
8: T
RANSMIT
T
ERMINATION
C
ONTROL
....................................................................................... 31
T
ABLE
9: T
ERMINATION
S
ELECT
C
ONTROL
.......................................................................................... 31
REDUNDANCY APPLICATIONS ............................................................................................................. 32
T
ABLE
10: T
RANSMIT
T
ERMINATION
C
ONTROL
..................................................................................... 32
T
ABLE
11: T
RANSMIT
T
ERMINATIONS
................................................................................................... 32
TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 33
Figure 16. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ....... 34
Figure 17. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy ............. 34
Figure 18. Simplified Block Diagram - Transmit Section for N+1 Redundancy ......................... 35
Figure 19. Simplified Block Diagram - Receive Section for N+1 Redundancy .......................... 36
P
ATTERN
T
RANSMIT
AND
D
ETECT
F
UNCTION
............................................................................................... 37
T
RANSMIT
A
LL
O
NES
(TAOS) .................................................................................................................... 37
N
ETWORK
L
OOP
C
ODE
D
ETECTION
AND
T
RANSMISSION
.............................................................................. 37
T
ABLE
12: P
ATTERN
TRANSMISSION
CONTROL
..................................................................................... 37
T
ABLE
13: L
OOP
-C
ODE
D
ETECTION
C
ONTROL
..................................................................................... 37
T
RANSMIT
AND
D
ETECT
Q
UASI
-R
ANDOM
S
IGNAL
S
OURCE
(TDQRSS) ......................................................... 38
L
OOP
-B
ACK
M
ODES
................................................................................................................................... 39
L
OCAL
A
NALOG
L
OOP
-B
ACK
(ALOOP) ....................................................................................................... 39
T
ABLE
14: L
OOP
-
BACK
CONTROL
IN
H
ARDWARE
MODE
........................................................................ 39
T
ABLE
15: L
OOP
-
BACK
CONTROL
IN
H
OST
MODE
................................................................................. 39
Figure 20. Local Analog Loop-back signal flow ........................................................................... 39
R
EMOTE
L
OOP
-B
ACK
(RLOOP) ................................................................................................................. 40
Figure 21. Remote Loop-back mode with jitter attenuator selected in receive path ................. 40
Figure 22. Remote Loop-back mode with jitter attenuator selected in Transmit path .............. 40
D
IGITAL
L
OOP
-B
ACK
(DLOOP) .................................................................................................................. 41
D
UAL
L
OOP
-B
ACK
...................................................................................................................................... 41
Figure 23. Digital Loop-back mode with jitter attenuator selected in Transmit path ................ 41
Figure 24. Signal flow in Dual loop-back mode ............................................................................ 41
MICROPROCESSOR PARALLEL INTERFACE .............................................................. 42
T
ABLE
16: M
ICROPROCESSOR
INTERFACE
SIGNAL
DESCRIPTION
........................................................... 42
M
ICROPROCESSOR
R
EGISTER
T
ABLES
........................................................................................................ 43
T
ABLE
17: M
ICROPROCESSOR
R
EGISTER
A
DDRESS
............................................................................. 43
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
................................................................. 43
M
ICROPROCESSOR
R
EGISTER
D
ESCRIPTIONS
............................................................................................. 46
T
ABLE
19: M
ICROPROCESSOR
R
EGISTER
#0, B
IT
D
ESCRIPTION
........................................................... 46
T
ABLE
20: M
ICROPROCESSOR
R
EGISTER
#1, B
IT
D
ESCRIPTION
........................................................... 47
T
ABLE
21: M
ICROPROCESSOR
R
EGISTER
#2, B
IT
D
ESCRIPTION
........................................................... 49
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
#3, B
IT
D
ESCRIPTION
........................................................... 51
T
ABLE
23: M
ICROPROCESSOR
R
EGISTER
#4, B
IT
D
ESCRIPTION
........................................................... 53
T
ABLE
24: M
ICROPROCESSOR
R
EGISTER
#5, B
IT
D
ESCRIPTION
........................................................... 54
T
ABLE
25: M
ICROPROCESSOR
R
EGISTER
#6, B
IT
D
ESCRIPTION
........................................................... 56
T
ABLE
26: M
ICROPROCESSOR
R
EGISTER
#7, B
IT
D
ESCRIPTION
........................................................... 57
T
ABLE
27: M
ICROPROCESSOR
R
EGISTER
#8, B
IT
D
ESCRIPTION
........................................................... 58
T
ABLE
28: M
ICROPROCESSOR
R
EGISTER
#9, B
IT
D
ESCRIPTION
........................................................... 58
T
ABLE
29: M
ICROPROCESSOR
R
EGISTER
#10, B
IT
D
ESCRIPTION
......................................................... 59
T
ABLE
30: M
ICROPROCESSOR
R
EGISTER
#11, B
IT
D
ESCRIPTION
......................................................... 59
T
ABLE
31: M
ICROPROCESSOR
R
EGISTER
#12, B
IT
D
ESCRIPTION
......................................................... 60
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83L34_05 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83L34ES 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83L34IV 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT83L34IV-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT83L34IVTR 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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