參數(shù)資料
型號(hào): XRT83L34
廠商: Exar Corporation
英文描述: QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述: 四T1/E1/J1收發(fā)左/上海收發(fā)器和時(shí)鐘恢復(fù)和抖動(dòng)衰減器
文件頁數(shù): 2/82頁
文件大?。?/td> 447K
代理商: XRT83L34
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
2
FEATURES
Fully integrated four channel long-haul or short-
haul transceivers for E1,T1 or J1 applications
Adaptive Receive Equalizer for up to 36dB cable
attenuation
Programable Transmit Pulse Shaper for E1,T1 or J1
short-haul interfaces
Five fixed transmit pulse settings for T1 short-haul
applications plus a fully programmable waveform
generator for transmit output pulse shaping that
can be used for both T1 and E1 modes.
Transmit Line Build-Outs (LBO) for T1 long-haul
application from 0dB to -22.5dB in three 7.5dB
steps
Selectable receiver sensitivity from 0 to 36dB cable
loss for T1 @772kHz and 0 to 43dB for E1
@1024kHz
Receive monitor mode handles 0 to 29dB resistive
attenuation along with 0 to 6dB of cable attenuation
for E1 and 0 to 3dB of cable attenuation for T1
modes
Supports 75
and 120
(E1), 100
(T1) and 110
(J1) applications
Internal and/or external impedance matching for
75
, 100
,
110
and 120
Tri-State transmit output and receive input
capability for redundancy applications
Provides High Impedance for Tx and Rx during
power off
Transmit return loss meets or exceeds ETSI 300-
166 standard
On-chip digital clock recovery circuit for high input
jitter tolerance
Crystal-less digital jitter attenuator with 32-bit or 64-
bit FIFO selectable either in transmit or receive path
On-chip frequency multiplier generates T1 or E1
Master clocks from variety of external clock sources
High receiver interference immunity
On-chip transmit short-circuit protection and
limiting, and driver fail monitor output (DMO)
Receive loss of signal (RLOS) output
On-chip
HDB3/B8ZS/AMI
functions
QRSS pattern generator and detection for testing
and monitoring
Error and Bipolar Violation Insertion and Detection
encoder/decoder
F
IGURE
2 B
LOCK
D
IAGRAM
OF
THE
XRT83L34 T1/E1/J1 LIU (H
ARDWARE
M
ODE
)
One of four Channels, CHANNEL_n - (n=0 : 3)
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
ICT
MCLKE1
MCLKT1
CLKSEL[2:0]
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
RTIP_n
RRING_n
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
DMO_n
TTIP_n
TRING_n
TXON_n
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
LOCAL
ANALOG
LOOPBACK
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
RX
EQUALIZER
EQUALIZER
CONTROL
AIS
DETECTOR
LOS
DETECTOR
LBO[3:0]
LOOPBACK
ENABLE
J
S
NLCD ENABLE
QRSS ENABLE
HARWARE CONTROL
TEST
RESET
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
DRIVE
MONITOR
DFM
MCLKOUT
TAOS_n
LOOP1_n
LOOP0_n
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