參數(shù)資料
型號: XRT83L34
廠商: Exar Corporation
英文描述: QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述: 四T1/E1/J1收發(fā)左/上海收發(fā)器和時鐘恢復(fù)和抖動衰減器
文件頁數(shù): 32/82頁
文件大?。?/td> 447K
代理商: XRT83L34
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
29
TRANSMIT AND RECEIVE TERMINATIONS
The XRT83L34 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the
use of existing components and/or designs.
RECEIVER (CHANNELS 0 - 3)
I
NTERNAL
R
ECEIVE
T
ERMINATION
M
ODE
In
Hardware
mode, RXTSEL (Pin 83) can be tied “High” to select internal termination mode for all receive
channels or tied “Low” to select external termination mode. Individual channel control can only be done in
Host
mode. By default the XRT83L34 is set for external termination mode at power up or at
Hardware
reset.
In
Host
mode, bit 7 in the appropriate channel register, (
Table 20, “Microprocessor Register #1, Bit
Description,” on page 47
), is set “High” to select the internal termination mode for that specific receive channel.
If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in
Table 7
.
N
OTE
:
In
Hardware
mode, pins RXRES[1:0] control all channels.
T
ABLE
6: R
ECEIVE
T
ERMINATION
C
ONTROL
RXTSEL
RX TERMINATION
0
EXTERNAL
1
INTERNAL
F
IGURE
13. S
IMPLIFIED
D
IAGRAM
FOR
THE
I
NTERNAL
R
ECEIVE
AND
T
RANSMIT
T
ERMINATION
M
ODE
T1
TTIP
TRING
5
8
1:2
75
, 100
110
or 120
4
1
0.68
μ
F
R
int
R
int
TTIP
TRING
TX
Line Driver
T2
RTIP
RRING
1
4
1:1
8
5
RTIP
RRING
RX
Equalizer
R
int
Channel _n
TPOS
TNEG
TCLK
RPOS
RNEG
RCLK
75
, 100
110
or 120
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