參數(shù)資料
型號(hào)： XR16C872
廠商： Exar Corporation
英文描述： Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）)
中文描述： 雙UART）與1284并行端口，插頭插即用（PnP）功能控制器（雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）
文件頁(yè)數(shù)： 48/60頁(yè)
文件大?。?/td> 314K
代理商： XR16C872
XR16C872
48
Rev. P1.00
Preliminary
Signal
Name
Signal
Type
ECP mode
Name
Description
STROBE#
O
HostClk
Used with PeriphAck to transfer data or address information in the
forward direction.
AUTOFD#
O
HostAck
Provides Command / Data status in the forward direction. Used with
PeriphClk to transfer data in the reverse direction.
SELCTIN#
O
1284Active
Set high when host is in a 1284 transfer mode.
INIT#
O
ReverseReq#
Driven low to put the channel in reverse direction.
ACK#
I
PeriphClk
Used with HostAck to transfer data in the reverse direction.
BUSY
I
PeriphAck
Used with HostClk to transfer data or address information in the
forward direction. Provides Command / Data status in the reverse
direction.
PE
I
AckReverse#
Driven low to acknowledge ReverseRequest.
SELECT
I
Xflag
Extensibility flag.
ERR#
I
PeriphReq#
Set low by peripheral to indicate that reverse dat is available.
PD0-PD7
I/O
D0-D7
Bi-directional data lines.
Table 11. ECP Mode Signal Description
ECP Mode Forward Data and Command Transfer Cycle
1. Host places data on the data lines and indicates a data cycle by setting HostAck high.
2. Host asserts HostClk low to indicate valid data.
3. Peripheral acknowledge host by setting PeriphAck high.
4. Host sets HostClk high. This is the edge that should be used to clock the data in to the peripheral.
5. Peripheral sets PeriphAck low to indicate that it is ready for the next byte.
6. The cycle repeats, but this time it is command cycle because HostAck is low.
ECP Mode Reverse Data and Command Transfer Cycle
1. The Host requests a reverse channel transfer by setting ReverseReq# low.
2. The peripheral signals that it is okay to proceed by setting AckReverse# low.
3. The peripheral places data on the data lines and indicates a data cycle by setting PeriphAck high.
4. Peripheral asserts PeriphClk low to indicate valid data.
5. Host acknowledges by setting HostAck high.
6. Peripheral sets PeriphClk high. This is the edge that should be used to clock the data in to the host.
7. Host sets HostAck low to indicate that it is ready for the next byte.
8. The cycle repeats, but this time it is a Command cycle because PeriphAck is low.
相關(guān)PDF資料
PDF描述
XR16L2450 2.25V TO 5.5V DUART
XR16L2450IJ 97-3108A20-29S-KIT
XR16L2450IM 2.25V TO 5.5V DUART
XR16L2550IJ LOW VOLTAGE DUART WITH 16-BYTE FIFO
XR16L2550IL LOW VOLTAGE DUART WITH 16-BYTE FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16C872CQ 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER
XR16C872IQ 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER
XR16L2450 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART
XR16L2450_05 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART
XR16L2450IJ 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*