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參數(shù)資料
| 型號： | XR16C872 |
| 廠商： | Exar Corporation |
| 英文描述： | Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）) |
| 中文描述： | 雙UART）與1284并行端口，插頭插即用（PnP）功能控制器（雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器） |
| 文件頁數(shù)： | 41/60頁 |
| 文件大?。?/td> | 314K |
| 代理商： | XR16C872 |
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XR16C872
41
Rev. P1.00
Preliminary
DCR Bit-4:
Ack Interrupt Enable set to a high will generate an
interrupt when ACK# is low. When either returns to a
high state, this interrupt source will go in-active. This
interrupt is not pulsed.
DCR Bit-5:
Peripheral port direction, OUT = 0 and IN = 1.
This bit is forced to logic zero by ECR modes 000 or
010. It can be written only in ECR mode 001, and will
maintain that state if the ECR mode is changed to 011,
100, or 110. This bit must be set low for EPP mode,
which allows the host to control direction with IOR# and
IOW#. The final port direction also drives PDIR.
DCR Bits 6-7:
Reserved, logic zero.
EPP ADDRESS PORT ( EPP-APort )
When EPP mode is enabled, a host read or write with
this port will result in a data transfer directly to/from the
peripheral with SLCTIN# active. Direction is set by
host read/write and will drive STROBE# low during a
write if DCR bit 5 (DIR) is not set high.
EPP DATA PORT (EPP-DPort )
When EPP mode is enabled, a host read or write with
this port will result in a data transfer directly to/from the
peripheral with AUTOFD# active. Direction is set by
host read/write and will drive STROBE# low during a
write if DCR bit 5 (DIR) is not set high.
PARALLEL PORT DATA ( C-FIFO )
This port is available for programmed I/O and DMA
access. Data written to this port is stored in the FIFO
if FIFO-F = 0 and will be lost if FIFO-F = 1.
Data written to this port will be automatically trans-
ferred to the peripheral with STROBE# handshaking
with BUSY. This port is only defined for write, host
reads will interfere with FIFO read sequencing.
ECP DATA FIFO ( ECP-DFIFO )
This port is available for programmed I/O and DMA
access. Data written to this port is stored in the FIFO
if FIFO-F = 0 and will be lost if FIFO-F = 1. A 9th FIFO
bit (tag) is set high on write.
Data read from this port will undergo de-compression if
the FIFO tag bit and data bit-7 are both low. The byte
containing the RLE count is loaded into the RLE
counter and the succeeding byte in the FIFO will be
returned to the host RLE count + 1 times before the
FIFO read address is incremented. If a FIFO under-run
is incurred during host read, the last data byte is
returned and FIFO-E remains coherent.
TEST FIFO ( T-FIFO )
This port is available for programmed I/O and DMA
access. Data written to this port is stored in the FIFO
if FIFO-F = 0 and will be lost if FIFO-F = 1. During a
read cycle from this port a FIFO under-run will return
last data read and FIFO-E remains coherent.
CONFIGURATION REGISTER A ( Cnfg-A )
This read-only register is available in ECR mode 111
only.
Cnfg-A Bit 0-1:
Forced to logic zero, this field is don’t care for PWord
= 1 byte.
Cnfg-A Bit-2:
When transmitting, there is 1 byte waiting to be trans-
mitted that does not affect FIFO-F.
Cnfg-A Bit-3:
Reserved, logic zero.
Cnfg-A Bit 4-6:
Indicates PWord = 1 byte (8-bit implementation).
Cnfg-A Bit-7:
Indicates ECP interrupts are pulsed.
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