參數(shù)資料
型號： XR16C872
廠商： Exar Corporation
英文描述： Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）)
中文描述： 雙UART）與1284并行端口，插頭插即用（PnP）功能控制器（雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）
文件頁數(shù)： 22/60頁
文件大?。?/td> 314K
代理商： XR16C872
XR16C872
22
Rev. P1.00
Preliminary
Figure 6. Clock Pre-scaler and Baud Rate Generator Circuitry
6 provide an indication when the transmitter is empty
or has an empty location(s). The user can optionally
operate the transmit and receive FIFOs in the DMA
mode (FCR bit-3). When transmit and receive FIFOs
are enabled and the DMA mode is deactivated (DMA
Mode “0”), the UART activates the interrupt output pin
for each data transmit or receive operation. When DMA
mode is activated (DMA Mode “1”), the user takes the
advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by
the preset trigger level. In this mode, the UART asserts
the interrupt output pin when characters in the transmit
FIFOs are below the transmit trigger level, or the
number of characters in the receive FIFOs are above
the receive trigger level. Transmit or receive DMA
operation is selected by EMSR register bit 2.
Sleep Mode
The UARTs are designed to operate with low power
consumption. A sleep mode is included to further
reduce power consumption when the chip is not being
used. The operating parameters are maintained while
in sleep. With EFR bit-4 and IER bit-4 enabled (set to
logic 1), the UART enters the sleep mode when no
interrupt is pending and no activities on the modem
port. If an external clock is supplied to the UART, you
The generator divides the input 16X clock by any
divisor from 1 to 2
16
clock by 16. Further division of this 16X clock provides
two table rates to support low and high data rate
applications using the same system design. The two
rate tables are selectable through the internal register,
MCR bit-7. Setting MCR bit-7 to logic 1 provides an
additional divide by 4 whereas, setting MCR bit-7 to
logic 0 only divides by 1. (See Table 3 and Figure 6).
The frequency of the internal sampling rate is exactly
16X (16 times) of the selected baud rate. Customized
Baud Rates can be achieved by selecting the proper
divisor values for the MSB and LSB sections of baud
rate generator.
-1. The UART divides the input
Programming the Baud Rate Generator Registers DLM
(MSB) and DLL (LSB) provides the user capability for
selecting the desired serial baud rate. Table 3 shows
the two selectable baud rate tables available with the
7.3728 MHz clock. The output data rate tolerance is
determined by the frequency accuracy of the
22.1184MHz crystal or external clock.
DMA Operation
The FIFO trigger level provides additional flexibility to
the user for data block transfer operation. LSR bits 5-
Baud Rate
Generator
Baud Clock to
Transmitter and
Receiver
MCR
Bit-7=0
(default)
MCR
Bit-7=1
7.3728 MHz.
Clock from Osc. &
Divider
Pre-scaler
Divides
by 1
DLM and DLL
Registers
Pre-scaler
Divides
by 4
相關(guān)PDF資料
PDF描述
XR16L2450 2.25V TO 5.5V DUART
XR16L2450IJ 97-3108A20-29S-KIT
XR16L2450IM 2.25V TO 5.5V DUART
XR16L2550IJ LOW VOLTAGE DUART WITH 16-BYTE FIFO
XR16L2550IL LOW VOLTAGE DUART WITH 16-BYTE FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16C872CQ 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER
XR16C872IQ 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER
XR16L2450 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART
XR16L2450_05 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART
XR16L2450IJ 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART
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