參數(shù)資料
型號(hào)： XR16C872
廠商： Exar Corporation
英文描述： Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）)
中文描述： 雙UART）與1284并行端口，插頭插即用（PnP）功能控制器（雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）
文件頁(yè)數(shù)： 13/60頁(yè)
文件大?。?/td> 314K
代理商： XR16C872
XR16C872
13
Rev. P1.00
Preliminary
FUNCTION DESCRIPTION
The XR16C872 (872) is a highly integrated chip com-
bining the functionality of two XR16C850 enhanced
UART, an IEEE 1284 bi-directional printer interface,
and the PC/ISA bus Plug-and-Play (PnP) interface.
The PnP interface meets the Plug-and-Play ISA Speci-
fication Version 1.0a of May 5,1994. The PnP interface
and the 1284 printer port are both clocked for maximum
performance by an external crystal oscillator of
22.1184 MHz. This clock is then internally divided by
three to obtain a 7.3728 MHz clock for the two UARTs.
CPU Bus Interface Options
The 872 has two data bus interface modes, PnP and
manual. In PnP mode, the chip will interface to the PC/
ISA bus directly and automatically configure each
UART and the1284 parallel port address and IRQ
interrupt. Figure 1, depicts the block diagram and
interface.
Plug-and-Play Mode
The PnP interface supports industry standard
jumperless auto configuration procedure in the PC/ISA
bus system. With an external EEPROM chip providing
the resource data for each of the logical devices, it
automatically negotiates with Windows
95 or 98
operating system and configures the operating setting
for each device.
The PC host system identifies and configures each
PnP device using a set of defined registers accessed
on the ISA bus through three 8-bit I/O ports. All PnP
interfaces in the host system respond to these same
I/O ports, so after first sending an initiation key in order
to enable all the interfaces, each interface is then
isolated through the Isolation Protocol. Even though all
interfaces initially respond to the Isolation Protocol,
the protocol is accomplished in such a way that no bus
contention will occur. After a given interface has been
isolated it is then assigned a unique Card Select
Number (CSN) so that there after the interface can be
uniquely addressed.
All PnP interfaces support a defined readable resource
data structure that completely describes the total
resources required and the options supported by the
interface. Resource requirements of each PnP inter-
face are broken down into groupings called Logical
Devices, each of which can be thought of as a separate
device. The two 850 UART and the 1284 parallel data
port are referred to as a logical device, for a total of
three logical devices. When all resource requirements
of the entire system are known, a process of resource
arbitration is invoked on the host system under Win-
dows operating system to determine the resources to
allocate to each device. Finally, each device’s re-
source usage is programmed through a set of configu-
ration registers. Some of these configuration registers
are common to all logical devices but the bulk of the
registers are accessed separately for each logical
device in the interface, with each particular logical
device’s configuration registers being mapped into the
PnP register set one at a time.
After configuration is complete, each PnP interface is
removed from configuration mode in order to prevent
accidental erasure or modification of the interface’s
configuration. To re-enable configuration mode, the
initiation key must be re-issued. The 872 uses all 16-
bit address lines (A0-A15) for address decoding and
supports 10 IRQ's (IRQ3-7, 9-12 and 15). Application
note #xxxx describes the operation of the PnP inter-
face in more detail.
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