- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376454 > XR16C872 (Exar Corporation) Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）) PDF資料下載
參數(shù)資料
| 型號： | XR16C872 |
| 廠商： | Exar Corporation |
| 英文描述： | Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）) |
| 中文描述： | 雙UART）與1284并行端口，插頭插即用（PnP）功能控制器（雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器） |
| 文件頁數(shù)： | 31/60頁 |
| 文件大?。?/td> | 314K |
| 代理商： | XR16C872 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
XR16C872
31
Rev. P1.00
Preliminary
An example to program the FIFO trigger level:
write LCR with 0xBF
set FCTR bit4-5 to logic 1 ; select trigger Table-D
set FCTR bit-7 to logic 0
write TRG with 0x60
set FCTR bit-7 to logic 1
write TRG with 0x08
write LCR with 0x03
; point to enhanced registers
; program RX FIFO trigger level
; set your RX trigger level to 96
; program TX FIFO trigger level
; set your TX trigger level to 8
; set operating parameters
Receive data ready interrupt will activates when RX
FIFO fills up to 96 data bytes while the transmit empty
interrupt gets set when data is empty to 8 bytes.
Interrupt Status Register (ISR)
The UART provides six levels of prioritized interrupts
to minimize external software interaction. The Interrupt
Status Register (ISR) provides the user with six inter-
rupt status bits. Performing a read cycle on the ISR will
provide the user with the highest pending interrupt level
to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the
interrupt status register is read, the interrupt status is
cleared. However it should be noted that only the
current pending interrupt is cleared by the read. A lower
level interrupt may be seen after re-reading the inter-
rupt status bits. The Interrupt Source Table 6 (below)
shows the data values (bit 0-5) for the six prioritized
interrupt levels, the interrupt sources associated with
each of these interrupt levels, and how to clear each
interrupt (INT).
Priority
Level
[ ISR BITS ]
INT Clears
After A
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Source of the Interrupt
1
2
2
3
4
5
6
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Rcv. Xoff signal / Special character)
CTS, RTS change of state
LSR read
LSR read
LSR read
ISR read
MSR read
ISR read
MSR read
Table 4. Interrupt Priority and Source
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16L2450 | 2.25V TO 5.5V DUART |
| XR16L2450IJ | 97-3108A20-29S-KIT |
| XR16L2450IM | 2.25V TO 5.5V DUART |
| XR16L2550IJ | LOW VOLTAGE DUART WITH 16-BYTE FIFO |
| XR16L2550IL | LOW VOLTAGE DUART WITH 16-BYTE FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C872CQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER |
| XR16C872IQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER |
| XR16L2450 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART |
| XR16L2450_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART |
| XR16L2450IJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。