參數(shù)資料
型號: XR16C872
廠商: Exar Corporation
英文描述: Dual UART with 1284 Parallel Port and Plug-and-Play(PnP) Controller(雙通用異步接收器/發(fā)送器(帶1284雙向并行端口和即插即用控制器))
中文描述: 雙UART)與1284并行端口,插頭插即用(PnP)功能控制器(雙通用異步接收器/發(fā)送器(帶1284雙向并行端口和即插即用控制器)
文件頁數(shù): 33/60頁
文件大?。?/td> 314K
代理商: XR16C872
XR16C872
33
Rev. P1.00
Preliminary
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive data.
LCR
Bit-3
LCR
Bit-4
LCR
Bit-5
Parity Selection
0
1
1
1
X
0
1
0
X
0
0
1
No parity
Odd parity
Even parity
Forced parity=“1”
1
1
1
Forced parity= 0”
LCR BIT-6:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
LCR BIT-7:
The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled. (normal default condi-
tion)
Logic 1 = Select baud rate divisors (DLL and DLM) and
enhanced feature register set enabled
Modem Control Register (MCR)
This register controls the interface with the modem or
a peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force RTS# output to a logic 1. (normal
default condition)
Logic 1 = Force RTS# output to a logic 0.
Automatic RTS may be used for hardware flow control
by enabling EFR bit-6 (See EFR bit-6).
MCR BIT-2:
*OP1# output is not available in the 872.
Logic 0 = Set OP1# output to a logic 1. (normal default
condition)
Logic 1 = Set OP1# output to a logic 0.
MCR BIT-3:
*OP2# output is not available in the 872
Logic 0 = Set OP2# output to a logic 1. (normal default
condition)
Logic 1 = Set OP2# output to a logic 0.
MCR BIT-4:
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
MCR BIT-5:
Logic 0 = Disable Xon-Any function (normal default
condition)
Logic 1 = Enable Xon-Any function. In this mode any
RX character received will enable Xon.
MCR BIT-6:
Logic 0 = Enable Modem receive and transmit input/
output interface. (normal default condition)
Logic 1 = Enable infrared IrDA receive and transmit
inputs/outputs. While in this mode, the TX/RX output/
inputs are routed to the infrared encoder/decoder. The
data input and output levels will conform to the IrDA
infrared interface requirement. As such, while in this
mode the infrared TX output will be a logic 0 during idle
data conditions. Care must be taken into consideration
in the design not to over heat the IR LED during power
up initialization state while TX output is still at logic 1.
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