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型號(hào)：	XPC801ZP25
元件分類：	微處理器
英文描述：	Microprocessor
中文描述：	微處理器
文件頁(yè)數(shù)：	397/605頁(yè)
文件大小：	2380K
代理商：	XPC801ZP25

Serial Communication Modules

MPC801 USER’S MANUAL

16.3.2.4.6 SPI Mask & Interrupt Level Register.

The 8-bit read/write SPI mask &

interrupt level register (SPIMR) contains the mask for the F and E bits in the SPIER and the

priority request level of the interrupt. If the mask bit in the SPIMR is 1, the corresponding

interrupt in the SPIER is enabled. If the proper mask bit is zero, the corresponding interrupt

in the SPIER is masked. This register is cleared at reset.

Bits 0–3—Reserved

These bits are reserved and should be set to zero.

SPIRL—SPI Interrupt Request Level

This field contains the priority request level of the interrupt request level 0-7.

If this bit is set to 1, the corresponding interrupt in the SPIER register is enabled. If it is zero,

the corresponding interrupt is masked.

E—Empty Mask

If this bit is set to 1, the corresponding interrupt in the SPIER register is enabled. If it is zero,

the corresponding interrupt is masked.

16.3.3 The I

C Controller

The inter-integrated circuit (I

C) controller allows the MPC801 to exchange data with other

C devices such as microcontrollers, EEPROMs, real-time clock devices, A/D converters,

and LCDs. The I

C controller is a synchronous, multimaster bus that is used to connect

several integrated circuits on a board. It uses two wires—serial data and serial clock—to

carry information between the integrated circuits connected to the bus.

C controller consists of transmitter and receiver sections, an independent baud rate

generator, and a control unit. The transmitter and receiver sections use the same clock,

which is derived from the I

C controller baud rate generator in master mode and generated

externally in slave mode. The MPC801 I

C most-significant bit is shifted out first. When the

C is not enabled in the I2MOD register, it consumes minimal power. Figure 4-5 illustrates

C controller block diagram.

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