
PowerPC Architecture Compliance
7-8
MPC801 USER’S MANUAL
MOTOROLA
7
7.3.6.3 TLB INVALIDATE ALL (tlbia)
This instruction is performed as defined by the architecture.
7.3.6.4 TLB SYNCHRONIZE (tlbsync)
This instruction is implemented like and functions like a regular
mtspr
instruction as it
relates to engine synchronization with no further effects.
7.3.7 Interrupts
7.3.7.1 CLASSES
All interrupts associated with storage are implemented as precise interrupts by the core,
which means that a load/store instruction is not complete until all possible error indications
are sampled from the load/store bus. This also implies that a store or nonspeculative load
instruction is not issued to the load/store bus until all previous instructions have completed.
If a late error occurs, a store cycle or a nonspeculative load cycle can be issued and aborted.
7.3.7.2 PROCESSING
In each interrupt handler, when SRR0 and SSR1 are saved, MSR
RI
can be set to 1.
7.3.7.3 DEFINITIONS
The following table defines the offset value by interrupt type and the sections that follow
describe each interrupt in detail.
Table 7-1. Offset of First Instruction by Interrupt Type
OFFSET (HEX)
INTERRUPT TYPE
00000
Reserved
00100
System Reset
00200
Machine Check
00300
Data Storage
00400
Instruction Storage
00500
External
00600
Alignment
00700
Program
00800
Floating Point Unavailable
00900
Decrementer
00A00
Reserved
00B00
Reserved
00C00
System Call
00D00
Trace
00E00
Floating Point Assist
01000
Implementation Dependent Software Emulation