
System Interface Unit
12-6
MPC801 USER’S MANUAL
MOTOROLA
12
12.3.2.1 PROGRAMMING THE INTERRUPT CONTROLLER.
interrupt controller contains the SIPEND, SIMASK, SIEL, and SIVEC registers.
The system interface unit
12.3.2.1.1 SIU Interrupt Pend Register.
contains bits that individually correspond to an interrupt request. The bits associated with
internal exceptions indicate, if set, that an interrupt service is requested. These bits reflect
the status of the internal requestor device and are cleared when the appropriate actions are
software-initiated in the device. Writing to these bits has no effect.
The 32-bit SIU interrupt pend (SIPEND) register
The bits associated with the IRQ pins have a different behavior, depending on the sensitivity
defined for them in the SIEL register. When the IRQ pin is defined as a “l(fā)evel” interrupt the
corresponding bit behaves similar to the bits associated with internal interrupt sources.
When the IRQ pin is defined as an “edge” interrupt and if the corresponding bit is set, it
indicates that a falling edge was detected on the signal. This bit is reset by writing a 1 to it.
IRQ—Interrupt Request 0–7
These bits reflect the status of the enternal interrupt requests.
0 = The appropriate interrupt service is not requested.
1 = The appropriate interrupt service is requested.
LVL—Level 0–7
These bits reflect the status of the internal requestor device.
0 = The appropriate interrupt service is not requested.
1 = The appropriate interrupt service is requested.
Bits 16–31—Reserved
These bits are reserved and should be set to 0.
SIPEND
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
IRQ0
LVL0
IRQ1
LVL1
IRQ2
LVL2
IRQ3
LVL3
IRQ4
LVL4
IRQ5
LVL5
IRQ6
LVL6
IRQ7
LV7
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIT
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIELD
RESERVED
RESET
0
R/W
R/W