
Serial Communication Modules
MOTOROLA
MPC801 USER’S MANUAL
16-13
16
16.2.1.4.4 Global Register.
UART block and resets to $0000.
This register contains global control and testing bits of the
Bits 0, 4–5, and 12—Reserved
These bits are reserved and should be set to zero.
CLSRC—Clock Source
This bit selects the source of the 1
bit clock is derived from the GPIO pin and must be configured as an input. When it is low
(normal), the bit clock is supplied by the baud rate generator. This bit allows high-speed
synchronous applications in which a clock is provided by the external system.
×
bit clock for transmit and receive. When it is high, the
0 = Bit clock is generated by baud rate generator.
1 = Bit clock is supplied by GPIO.
FPERR—Force Parity Errors
When this bit is high, it forces the transmitter to generate parity errors if parity is enabled.
This bit is provided for system debugging.
0 = Generate normal parity.
1 = Generate a parity error.
Table 16-1. Typical Baud Rates of Asynchronous Communication
BAUD
RATES
MPC801 SYSTEM FREQUENCY (MHZ)
20
24.5760
33
DIVIDER
PRE-
SCALER
ACTUAL
FREQUENCY
DIVIDER
PRE-
SCALER
ACTUAL
FREQUENCY
DIVIDER
PRE-
SCALER
ACTUAL
FREQUENCY
300
7
32
295.93
7
25
300
7
11
298.39
600
6
32
591.85
6
25
600
6
11
596.79
1,200
5
32
1183.7
5
25
1200
5
11
1193.6
2,400
4
32
2367.4
4
25
2400
4
11
2387.2
4,800
3
32
4735
3
25
4800
3
11
4774
9,600
2
32
9470
2
25
9600
2
11
9549
19,200
1
32
18939
1
25
19200
1
11
19097
38,400
0
32
37879
0
25
38400
0
11
38194
57,600
0
43
56818
0
38
56889
0
29
57292
115,200
0
54
113636
0
52
118154
0
47
114583
NOTE: All Values Are Decimal.
GLOBAL
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
RES
CLSRC
FPERR
LOOP
RESERVED
RXPOL
TXPOL
RTSC
RTS
IRDEN
IRDAL
RES
UIPL [0:2]
RESET
: $E000