
System Interface Unit
12-12
MPC801 USER’S MANUAL
MOTOROLA
12
Figure 12-4. RTC Block Diagram
12.8 THE PERIODIC INTERRUPT TIMER
The periodic interrupt timer (PIT) consists of a 16-bit counter clocked by a pitrtclk clock
supplied by the clock module. It decrements to zero when loaded with a value from the
periodic interrupt timer count (PITC) register and after the timer reaches zero, the PS bit is
set and an interrupt is generated if the PIE bit is a logic 1. At the next input clock edge, the
value in the PITC register is loaded into the counter and the process starts all over again.
When a new value is loaded into the PITC register, the periodic interrupt timer is updated,
the divider is reset, and the counter starts counting. If the PS bit is not cleared, it generates
an interrupt at the interrupt controller and the interrupt remains pending until it is cleared. If
the PS bit is set again, prior to being cleared, the interrupt remains pending until the PS bit
is cleared. Any write to the PITC register stops the current countdown and the count
resumes with a new value in the PITC. If the PTE bit is not set, the periodic interrupt timer
is unable to count and retains the old count value. Reads of the periodic interrupt timer have
no effect on it.
Figure 12-5. Periodic Interrupt Timer Block Diagram
pitrtclk
CLOCK
FREEZE
DIVIDE
BY 8,192
32-BIT COUNTER
32-BIT REGISTER
SEC
ALARM
INTERRUPT
=
CLOCK
DISABLE
DIVIDE
BY 9,600
MUX
38K
INTERRUPT
RTSEC
CLOCK
DISABLE
FREEZE
16-BIT
MODULUS
COUNTER
PERIODIC INTERRUPT
TIMER COUNT REGISTER
pitrtclk
CLOCK
PS
PIE
PIT
PTE
INTERRUPT