參數(shù)資料
型號： XC3S1400AN-4FGG484I
廠商： Xilinx Inc
文件頁數(shù)： 65/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 484FPGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-3AN
LAB/CLB數(shù)： 2816
邏輯元件/單元數(shù)： 25344
RAM 位總計： 589824
輸入/輸出數(shù)： 372
門數(shù)： 1400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
46
LVCMOS12
Slow
2
17
40
4
–13
–25
6
–10
–18
Fast
2
12
9
31
4
–9
–13
6
–9
QuietIO
2
36
55
4
–33
–36
6
–27
–36
PCI33_3
9
16
PCI66_3
–9
–13
HSTL_I
–11
–20
HSTL_III
–7
–8
HSTL_I_18
13
17
HSTL_II_18
–5
HSTL_III_18
8
10
8
SSTL18_I
7
13
7
15
SSTL18_II
–9
SSTL2_I
10
18
SSTL2_II
–6
–9
SSTL3_I
7
8
10
SSTL3_II
5
6
7
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
8
–22
–
LVDS_33
8
–27
–
BLVDS_25
1
4
MINI_LVDS_25
8
–22
–
MINI_LVDS_33
8
–27
–
LVPECL_25
Input Only
LVPECL_33
Input Only
RSDS_25
8
–22
–
RSDS_33
8
–27
–
TMDS_33
8
–27
–
PPDS_25
8
–22
–
Table 32: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair (Cont’d)
Signal Standard
(IOSTANDARD)
Package Type
TQG144
FTG256,
FGG400,
FGG484,
FGG676
Top,
Bottom
Banks 0,2
Left,
Right
Banks 1,3
Top,
Bottom
Banks 0,2
Left,
Right
Banks 1,3
PPDS_33
8
–27
–
DIFF_HSTL_I
–5
–10
DIFF_HSTL_III
–3
–4
DIFF_HSTL_I_18
6
8
DIFF_HSTL_II_18
–2
DIFF_HSTL_III_18
4
5
4
DIFF_SSTL18_I
3
6
3
7
DIFF_SSTL18_II
–4
DIFF_SSTL2_I
5
9
DIFF_SSTL2_II
–3
–4
DIFF_SSTL3_I
3
4
5
DIFF_SSTL3_II
2
3
Notes:
1.
Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS, RSDS,
PPDS, miniLVDS, and TMDS, are only supported in top or bottom
banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
2.
The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the VIL/VIH voltage
limits for the respective I/O standard.
3.
If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
Table 32: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair (Cont’d)
Signal Standard
(IOSTANDARD)
Package Type
TQG144
FTG256,
FGG400,
FGG484,
FGG676
Top,
Bottom
Banks 0,2
Left,
Right
Banks 1,3
Top,
Bottom
Banks 0,2
Left,
Right
Banks 1,3
相關(guān)PDF資料
PDF描述
7-745129-4 CONN FERRULE CRIMP DB 3,5
5748271-1 CONN SCREW LOCKS FMALE KIT 4-40
7-745129-9 CONN FERRULE CRIMP DB9,15,50
1-750877-9 CONN TERM COVER 100POS .050
ABB100DHLD CONN EDGECARD 200PS .050 DIP SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3S1400AN-4FGG676C 功能描述:IC SPARTAN-3AN FPGA 1400K 676FBG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
XC3S1400AN-4FGG676CES 制造商:Xilinx 功能描述:
XC3S1400AN-4FGG676I 功能描述:IC FPGA SPARTAN-AN 1400K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC3S1400AN-5FG484C 制造商:Xilinx 功能描述:SPARTAN3AN - Trays 制造商:Xilinx 功能描述:IC FPGA 372 I/O 484FBGA
XC3S1400AN-5FG676C 制造商:Xilinx 功能描述:FPGA SPARTAN-3AN FAMILY 1.4M GATES 25344 CELLS 770MHZ 90NM T - Trays 制造商:Xilinx 功能描述:IC FPGA 502 I/O 676FBGA 制造商:Xilinx 功能描述:IC SPARTAN-3AN FPGA 1400K 676BGA
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*