參數資料
型號: XC3S1400AN-4FGG484I
廠商: Xilinx Inc
文件頁數: 58/123頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3AN 484FPGA
標準包裝: 60
系列: Spartan®-3AN
LAB/CLB數: 2816
邏輯元件/單元數: 25344
RAM 位總計: 589824
輸入/輸出數: 372
門數: 1400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA
供應商設備封裝: 484-FBGA
Spartan-3AN FPGA Family: Introduction and Ordering Information
DS557 (v4.1) April 1, 2011
Product Specification
4
Configuration
Spartan-3AN FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored on-chip in nonvolatile Flash
memory, or externally in a PROM or some other nonvolatile
medium, either on or off the board. After applying power, the
configuration data is written to the FPGA using any of seven
different modes:
Configure from internal SPI Flash memory (Figure 2)
Completely self-contained
Reduced board space
Easy-to-use configuration interface
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an external
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary-Scan (JTAG), typically downloaded from a
processor or system tester
The MultiBoot feature stores multiple configuration files in
the on-chip Flash, providing extended life with field
upgrades. MultiBoot also supports multiple system
solutions with a single board to minimize inventory and
simplify the addition of new features, even in the field.
Flexibility is maintained to do additional MultiBoot
configurations via the external configuration method.
The Spartan-3AN device authentication protocol prevents
cloning. Design cloning, unauthorized overbuilding, and
complete reverse engineering have driven device security
requirements to higher and higher levels. Authentication
moves the security from bitstream protection to the next
generation of design-level security protecting both the
design and embedded microcode. The authentication
algorithm is entirely user defined, implemented using FPGA
logic. Every product, generation, or design can have a
different algorithm and functionality to enhance security.
In-System Flash Memory
Each Spartan-3AN FPGA contains abundant integrated SPI
serial Flash memory, shown in Table 3, used primarily to
store the FPGA’s configuration bitstream. However, the
Flash memory array is large enough to store at least two
MultiBoot FPGA configuration bitstreams or nonvolatile
data required by the FPGA application, such as
code-shadowed MicroBlaze processor applications.
After configuration, the FPGA design has full access to the
in-system Flash memory via an internal SPI interface; the
control logic is implemented with FPGA logic. Additionally,
the FPGA application itself can store nonvolatile data or
provide live, in-system Flash updates.
The Spartan-3AN device in-system Flash memory supports
leading-edge serial Flash features.
Small page size (264 or 528 bytes) simplifies
nonvolatile data storage
Randomly accessible, byte addressable
Up to 66 MHz serial data transfers
SRAM page buffers
Read Flash data while programming another Flash
page
EEPROM-like byte write functionality
Two buffers in most devices, one in XC3S50AN
Page, Block, and Sector Erase
X-Ref Target - Figure 2
Figure 2: Spartan-3AN FPGA Configuration Interface from Internal SPI Flash Memory
M2
M1
M0
VCCAUX
INIT_B
DONE
Spartan-3AN FPGA
‘0’
‘1’
3.3V
Configure
from internal
flash memory
Indicates when
configuration is
finished
DS557-1_06_082810
Table 3: Spartan-3AN Device In-System Flash Memory
Part Number
Total Flash
Memory
(Bits)
FPGA
Bitstream
(Bits)
Additional
Flash
Memory
(Bits)(1)
XC3S50AN
1,081,344
437,312
642,048
XC3S200AN
4,325,376
1,196,128
3,127,872
XC3S400AN
4,325,376
1,886,560
2,437,248
XC3S700AN
8,650,752
2,732,640
5,917,824
XC3S1400AN
17,301,504
4,755,296
12,545,280
Notes:
1.
Aligned to next available page location.
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