參數(shù)資料
型號: XC3S1400AN-4FGG484I
廠商: Xilinx Inc
文件頁數(shù): 112/123頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3AN 484FPGA
標準包裝: 60
系列: Spartan®-3AN
LAB/CLB數(shù): 2816
邏輯元件/單元數(shù): 25344
RAM 位總計: 589824
輸入/輸出數(shù): 372
門數(shù): 1400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA
供應商設備封裝: 484-FBGA
Spartan-3AN FPGA Family: Pinout Descriptions
DS557 (v4.1) April 1, 2011
Product Specification
89
XC3S50AN Differential I/O Alignment Differences
Also, some differential I/O pairs on the XC3S50AN FPGA are aligned differently than the corresponding pairs on the
XC3S200AN or XC3S400AN FPGAs, as shown in Table 74. All the mismatched pairs are in I/O Bank 2. The N side of each
pair is shaded.
XC3S50AN Does Not Have BPI Mode Address Outputs
The XC3S50AN FPGA does not generate the BPI-mode address pins during configuration. Table 75 summarizes these
differences.
The Spartan-3AN FPGAs are pin compatible with the same density Spartan-3A FPGAs in the FT(G)256 package, although
the Spartan-3A FPGAs require an external configuration source.
Table 74: Differential I/O Differences in FTG256
FTG256 Ball
Bank
XC3S50AN
XC3S200AN or XC3S400AN
T3
2
IO_L04P_2/VS2
IO_L03N_2/VS2
N6
IO_L03N_2/VS1
IO_L04P_2/VS1
R5
IO_L06P_2
IO_L05N_2
T5
IO_L05N_2/D7
IO_L06P_2/D7
P10
IO_L14P_2/MOSI/CSI_B
IO_L14N_2/MOSI/CSI_B
T10
IO_L14N_2
IO_L14P_2
R13
IO_L20P_2
IO_L18N_2
T14
IO_L18N_2
IO_L20P_2
Table 75: XC3S50AN BPI Functional Differences
FTG256 Ball
Bank
XC3S50AN
XC3S200AN or XC3S400AN
N16
1
IO_L03N_1
IO_L03N_1/A1
P16
IO_L03P_1
IO_L03P_1/A0
J13
IO_L10N_1
IO_L10N_1/A9
J12
IO_L10P_1
IO_L10P_1/A8
F13
IO_L20N_1
IO_L20N_1/A19
E14
IO_L20P_1
IO_L20P_1/A18
D15
IO_L22N_1
IO_L22N_1/A21
D16
IO_L22P_1
IO_L22P_1/A20
D14
IO_L23N_1
IO_L23N_1/A23
E13
IO_L23P_1
IO_L23P_1/A22
C15
IO_L24N_1
IO_L24N_1/A25
C16
IO_L24P_1
IO_L24P_1/A24
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