- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄202134 > W25Q32BVZEAG (WINBOND ELECTRONICS CORP) 32M X 1 SPI BUS SERIAL EEPROM, PDSO8 PDF資料下載
參數(shù)資料
| 型號(hào)： | W25Q32BVZEAG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 32M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 8 X 6 MM, GREEN, WSON-8 |
| 文件頁數(shù)： | 20/79頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | W25Q32BVZEAG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
W25Q32BV
Publication Release Date: April 01, 2011
- 27 -
Revision F
DO
(IO
1)
7.2.10 Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the
CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous
stream of data. This means that the entire memory can be accessed with a single instruction as long as
the clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in Figure 9. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR
(see AC Electrical Characteristics).
/CS
CLK
DI
(IO
0)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (03h)
High Impedance
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
7
6
5
4
3
2
1
0
7
24-Bit Address
23
22
21
3
2
1
0
Data Out 1
*
= MSB
*
Figure 9. Read Data Instruction Sequence Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3EG6466S335AD4M | 64M X 64 DDR DRAM MODULE, 0.7 ns, DMA200 |
| W3EG7264S335AD4SG | 64M X 72 DDR DRAM MODULE, 0.7 ns, DMA200 |
| WF1M32B-120G2UI3A | 1M X 32 FLASH 3.3V PROM MODULE, 120 ns, CQFP68 |
| WF1M32B-120H1I3A | 1M X 32 FLASH 3.3V PROM MODULE, 120 ns, CPGA66 |
| WE128K32N-150G2TC | 128K X 32 EEPROM 5V MODULE, 125 ns, CQFP68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q32BVZEAP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q32BVZEIG | 制造商:Winbond Electronics Corp 功能描述:32MB SPI FLASH |
| W25Q32BVZEIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q32BVZPAG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q32BVZPAP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。