- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄245706 > W19B160BTBBM (WINBOND ELECTRONICS CORP) 1M X 16 FLASH 2.7V PROM, 11 ns, PBGA48 PDF資料下載
參數(shù)資料
| 型號： | W19B160BTBBM |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 2.7V PROM, 11 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-48 |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 534K |
| 代理商： | W19B160BTBBM |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
W19B160BT/B DATA SHEET
Publication Release Date:Jan.04, 2008
- 15 -
Revision A5
with the initial two unlock cycles required in the standard program command sequence, resulting in
faster total programming time. Command Definitions shows the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-pass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the
data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Program/Erase operation refer Program Algorithm and Erase Algorithm illustration.
6.3
WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ5, DQ6,
and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase
operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY,
to determine whether an Embedded Program or Erase operation is in progress or has been
completed.
6.3.1
DQ7: #Data Polling
The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in
progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the
command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data
programmed to DQ7. When the Embedded Program algorithm is complete, the device outputs the
data programmed to DQ7. The system must provide the program address to read valid status
information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is
active for about 1S, and then the device returns to the read mode.
During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7.Once the Embedded
Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the
sectors selected for erasure must be provided to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, #Data
Polling on DQ7 is active for about 100S, and then the device returns to the read mode. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected. However, if the system reads DQ7 at an address
within a protected sector, the status may not be valid.
Just before the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when it samples the
DQ7 output, the system may read the status or valid data. Even if the device has completed the
program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still
invalid. Valid data on DQ7-DQ0 will appear on successive read cycles.
6.3.2
RY/#BY: Ready/#Busy
The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is
in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W7MG21M32SVB70BNC | 2M X 32 FLASH 3.3V PROM MODULE, 70 ns, SMA80 |
| W3EG7264S202AD4 | DDR DRAM MODULE, DMA200 |
| W3E232M16S-200STIG | 64M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| W3E232M16S-400STI | 64M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| W3EG6418S263D3 | 16M X 64 DDR DRAM MODULE, 0.75 ns, DMA184 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W19B160BTBH7H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:16Mbit, 2.7~3.6 volt CMOS flash memory |
| W19B160BTBM7H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:16Mbit, 2.7~3.6 volt CMOS flash memory |
| W19B160BTT7H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2.7~3.6-volt write (program and erase) operations, Fast write operation |
| W19B160TB7H7H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:16Mbit, 2.7~3.6 volt CMOS flash memory |
| W19B160TB7M7H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:16Mbit, 2.7~3.6 volt CMOS flash memory |
發(fā)布緊急采購，3分鐘左右您將得到回復。