參數(shù)資料
型號： VT8231
廠商： Electronic Theatre Controls, Inc.
元件分類： 晶體
英文描述： CRYSTAL 8.00MHZ 18PF SMD
中文描述： 南橋伏特，PC99柔順
文件頁數(shù)： 92/132頁
文件大?。?/td> 1210K
代理商： VT8231
VT8231
Preliminary Revision 0.8
October 29, 1999
-
86-
Function 4 Regs - Power Management, SMBus and HWM
7HFKQRORJLHV,QF
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Offset 4B-48
–
Power Management I/O Base ................. RW
31-16 Reserved
........................................ always reads 0
15-7 Power Management I/O Register Base Address.
Port Address for the base of the 128-byte Power
Management I/O Register block, corresponding to
AD[15:7]. The "I/O Space" bit at offset 41 bit-7
enables access to this register block. The definitions
of the registers in the Power Management I/O
Register Block are included later in this document,
following the Power-Management-Specific PCI
Configuration register descriptions and the Power
Management Subsystem overview.
6-0
0000001b
Offset 4C
–
Host Bus Power Management Control ....... RW
7-4
Thermal Duty Cycle (THM_DTY)
This 4-bit field determines the duty cycle of the
STPCLK# signal when the THRM# pin is asserted
low. The field is decoded as follows:
0000 Reserved.................................................default
0001 0-6.25%
0010 6.25-12.50%
0011 18.75-25.00%
0100 31.25-37.50%
0101 37.50-43.75%
0110 43.75-50.00%
0111 50.00-56.25%
1000 56.25-62.50%
1001 62.50-68.75%
1010 68.75-75.00%
1011 75.00-87.50%
1100 75.00-81.25%
1101 81.25-87.50%
1110 87.50-93.75%
1111 93.75-100%
3
THRM Enable
0
Disable ...................................................default
1
Enable
2
Frame Input as Resume Event in C3
0
Disable ...................................................default
1
Enable
1
Reserved
........................................ always reads 0
0
CPU Stop Grant Cycle Select
0
From Halt and Stop Grant Cycle............default
1
From Stop Grant Cycle
This bit is combined with I/O space Rx2C[3] for
controlling the start of CPUSTP# assertion during
system suspend mode:
Rx2C[3]
Rx4C[0]
Function 4
Function 4
I/O Space
Cfg Space
0
x
1
0
CPUSTP# Assertion
Immediate
Wait for CPU Halt
/ Stop Grant cycle
Wait for CPU
Stop Grant cycle
1
1
Offset 4D
–
Throttle / Clock Stop Control ..................... RW
7
Throttle Timer Reset
......................................def = 0
6-5
Throttle Timer
0x 4-Bit ....................................................default
10 3-Bit
11 2-Bit
4
Fast Clock (7.5us) as Throttle Timer Tick
0
Disable...................................................default
1
Enable
3
Reserved
........................................always reads 0
2
Internal Clock Stop for PCI Idle
0
Disable...................................................default
1
Enable
1
Internal Clock Stop During C3
0
Disable...................................................default
1
Enable
0
Internal Clock Stop During Suspend
0
Disable...................................................default
1
Enable
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