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參數(shù)資料
| 型號(hào)： | VT8231 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 晶體 |
| 英文描述： | CRYSTAL 8.00MHZ 18PF SMD |
| 中文描述： | 南橋伏特，PC99柔順 |
| 文件頁數(shù)： | 51/132頁 |
| 文件大?。?/td> | 1210K |
| 代理商： | VT8231 |
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VT8231
Preliminary Revision 0.8
October 29, 1999
-
45-
Register Descriptions - Legacy I/O Ports
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Interrupt Controller Registers
Ports 20-21 - Master Interrupt Controller
The Master Interrupt Controller controls system interrupt
channels 0-7. Two registers control the Master Interrupt
Controller. They are:
I/O Address Bits 15-0
Register Name
0000 0000 001x xxx0
Master Interrupt Control
0000 0000 001x xxx1
Master Interrupt Mask
RW
RW
Note that not all bits of the address are decoded.
The Master Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports A0-A1 - Slave Interrupt Controller
The Slave Interrupt Controller controls system interrupt
channels 8-15. The slave system interrupt controller also
occupies two register locations:
I/O Address Bits 15-0
Register Name
0000 0000 101x xxx0
Slave Interrupt Control
0000 0000 101x xxx1
Slave Interrupt Mask
RW
RW
Note that not all address bits are decoded.
The Slave Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Interrupt Controller Shadow Registers
The following shadow registers are enabled by setting function
0 Rx47[4]. If the shadow registers are enabled, they are read
back at the indicated I/O port instead of the standard interrupt
controller registers (writes are unchanged).
Port 20 - Master Interrupt Control Shadow ................... RO
Port A0 - Slave Interrupt Control Shadow ..................... RO
7
Reserved
........................................always reads 0
6
OCW3 bit 2 (POLL)
5
OCW3 bit 0 (RIS)
4
OCW3 bit 5 (SMM)
3
OCW2 bit 7 (R)
2
ICW4 bit 4 (SFNM)
1
ICW4 bit 1 (AEOI)
0
ICW1 bit 3 (LTIM)
Port 21 - Master Interrupt Mask Shadow ....................... RO
Port A1 - Slave Interrupt Mask Shadow ........................ RO
7-5
Reserved
........................................always reads 0
4-0
T7-T3 of Interrupt Vector Address
Timer / Counter Registers
Ports 40-43 - Timer / Counter Registers
There are 4 Timer / Counter registers:
I/O Address Bits 15-0
0000 0000 010x xx00
0000 0000 010x xx01
0000 0000 010x xx10
0000 0000 010x xx11
Register Name
Timer / Counter 0 Count
Timer / Counter 1 Count
Timer / Counter 2 Count
Timer / Counter Cmd Mode
RW
RW
RW
WO
Note that not all bits of the address are decoded.
The Timer / Counters are compatible with the Intel 8254
Timer / Counter chip. Detailed descriptions of 8254 Timer /
Counter operation can be obtained from the Intel Peripheral
Components Data Book and numerous other industry
publications.
Timer / Counter Shadow Registers
The following shadow registers are enabled for readback by
setting function 0 Rx47[4]. If the shadow registers are
enabled, they are read back at the indicated I/O port instead of
the standard timer / counter registers (writes are unchanged).
Port 40
–
Counter 0 Base Count Value (LSB 1
st
MSB 2
nd
) RO
Port 41
–
Counter 1 Base Count Value (LSB 1
st
MSB 2
nd
) RO
Port 42
–
Counter 2 Base Count Value (LSB 1
st
MSB 2
nd
) RO
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