
VT8231
Preliminary Revision 0.8
October 29, 1999
-
71-
Function 1 Registers - Enhanced IDE Controller
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IDE-Controller-Specific Confiiguration Registers
Offset 40 - Chip Enable .................................................... RW
7-4
Reserved
........................................ always reads 0
3-2
Reserved (Do Not Program)
...........R/W, default = 0
1
Primary Channel Enable
........ default = 0 (disabled)
0
Secondary Channel Enable
.... default = 0 (disabled)
Offset 41 - IDE Configuration ......................................... RW
7
Primary IDE Read Prefetch Buffer
0
Disable ...................................................default
1
Enable
6
Primary IDE Post Write Buffer
0
Disable ...................................................default
1
Enable
5
Secondary IDE Read Prefetch Buffer
0
Disable ...................................................default
1
Enable
4
Secondary IDE Post Write Buffer
0
Disable ...................................................default
1
Enable
3
Reserved
........................................ always reads 0
2
1
Reserved (Do Not Change)
........................ default=1
Reserved (Do Not Change)
........................ default=1
0
Reserved
........................................ always reads 0
Offset 42 - Reserved (Do Not Program) .......................... RW
Offset 43 - FIFO Configuration ...................................... RW
7-4
Reserved
........................................always reads 0
3-2
Threshold for Primary Channel
00 0
01 1/4
10 1/2
....................................................default
11 3/4
1-0
Threshold for Secondary Channel
00 0
01 1/4
10 1/2
....................................................default
11 3/4