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參數(shù)資料
| 型號(hào)： | VT8231 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類(lèi)： | 晶體 |
| 英文描述： | CRYSTAL 8.00MHZ 18PF SMD |
| 中文描述： | 南橋伏特，PC99柔順 |
| 文件頁(yè)數(shù)： | 16/132頁(yè) |
| 文件大?。?/td> | 1210K |
| 代理商： | VT8231 |
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VT8231
Preliminary Revision 0.8
October 29, 1999
-10-
Pinouts
7HFKQRORJLHV,QF
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Pin Descriptions
Table 1. Pin Descriptions
PCI Bus Interface
Signal Name
Pin #
I/O
Signal Description
AD[31:0]
(see pin
list)
C5, D6,
A8, F10
F6
IO
Address/Data Bus.
The standard PCI address and data lines. The address is driven with
FRAME# assertion and data is driven or received in following cycles.
Command/Byte Enable.
The command is driven with FRAME# assertion. Byte
enables corresponding to supplied or requested data are driven on following clocks.
Frame.
Assertion indicates the address phase of a PCI transfer. Negation indicates that
one more data transfer is desired by the cycle initiator.
Initiator Ready.
Asserted when the initiator is ready for data transfer.
Target Ready.
Asserted when the target is ready for data transfer.
Stop.
Asserted by the target to request the master to stop the current transaction.
Device Select.
The VT8231 asserts this signal to claim PCI transactions through positive
or subtractive decoding. As an input, DEVSEL# indicates the response to a VT8231-
initiated transaction and is also sampled when decoding whether to subtractively decode
the cycle.
Parity.
A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
System Error.
SERR# can be pulsed active by any PCI device that detects a system
error condition. Upon sampling SERR# active, the VT8231 can be programmed to
generate an NMI to the CPU.
PCI Interrupt Request
. These pins are typically connected to the PCI bus INTA#-
INTD# pins as follows:
PINTA#
PINTB#
PCI Slot 1
INTA#
INTB#
PCI Slot 2
INTB#
INTC#
PCI Slot 3
INTC#
INTD#
PCI Slot 4
INTD#
INTA#
PCI Slot 5
INTA#
INTB#
PCI Request.
This signal goes to the North Bridge to request the PCI bus.
PCI Grant.
This signal is driven by the North Bridge to grant PCI access to the
VT8231.
PCI Request.
This signal goes to the North Bridge to request the PCI bus.
PCI Grant.
This signal is driven by the North Bridge to grant PCI access to the
VT8231.
PCI Clock.
PCLK provides timing for all transactions on the PCI Bus.
PCI Bus Clock Run.
This signal indicates whether the PCI clock is or will be stopped
(high) or running (low). The VT8231 drives this signal low when the PCI clock is
running (default on reset) and releases it when it stops the PCI clock. External devices
may assert this signal low to request that the PCI clock be restarted or prevent it from
stopping. Connect this pin to ground using a 100
resistor if the function is not used.
Refer to the
“
PCI Mobile Design Guide
”
and the VIA
“
Apollo MVP4 Design Guide
”
for
more details.
PCI Reset.
PCI Stop.
CPU Stop.
C/BE[3:0]#
IO
FRAME#
IO
IRDY#
TRDY#
STOP#
DEVSEL#
C7
B7
D7
A7
IO
IO
IO
IO
PAR
SERR#
C8
E7
IO
I
PINTA-D#
B2, B1,
C3, C2
I
PINTC#
INTC#
INTD#
INTA#
INTB#
INTC#
PINTD#
INTD#
INTA#
INTB#
INTC#
INTD#
PREQH#
PGNTH#
C1
D3
O
I
PREQL#
PGNTL#
D2
D1
O
I
PCICLK
PCKRUN#
M17
V1
I
IO
PCIRST#
PCISTP#
/ GPO6
CPUSTP#
/ GPO5
E4
W1
W2
O
O
O
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