參數(shù)資料
型號: V54C316162VAT10
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 1M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO50
封裝: 0.400 INCH, PLASTIC, TSOP2-50
文件頁數(shù): 45/61頁
文件大小: 916K
代理商: V54C316162VAT10
5
V54C316162VA Rev. 1.0 January 1998
MOSEL VITELIC
V54C316162VA
Operation Definition
All of SDRAM operations are defined by states of
control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows
the most important operation commands.
Mode Register
For application flexibility, a CAS latency, a burst
length, and a burst sequence can be programmed in
the SDRAM mode register. The mode set operation
must be done before any activate command after
the initial power up. Any content of the mode register
can be altered by re-executing the mode set com-
mand. Both banks must be in precharged state and
CKE must be high at least one clock before the
mode set operation. After the mode register is set, a
Standby or NOP command is required. Low signals
of RAS, CAS, and WE at the positive edge of the
clock activate the mode set operation. Address input
data at this timing defines parameters to be set as
shown in the following table.
Operation
CS
RAS
CAS
WE
(L/U)DQM
Standby, Ignore RAS, CAS, WE and Address
H
X
Row Address Strobe and Activating a Bank
L
H
X
Column Address Strobe and Read Command
L
H
L
H
X
Column Address Strobe and Write Command
L
H
L
X
Precharge Command
L
H
L
X
Burst Stop Command
L
H
L
X
Self Refresh Entry
L
H
X
Mode Register Set Command
L
X
Write Enable/Output Enable
X
L
Write Inhibit/Output Disable
X
H
No Operation (NOP)
L
H
X
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V54C316162VC-55 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-6 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-7 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16