參數(shù)資料
型號: V54C316162VAT10
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 1M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO50
封裝: 0.400 INCH, PLASTIC, TSOP2-50
文件頁數(shù): 13/61頁
文件大?。?/td> 916K
代理商: V54C316162VAT10
20
V54C316162VA Rev. 1.0 January 1998
MOSEL VITELIC
V54C316162VA
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 1, 2, 3)
7. Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 1, 2, 3)
COMMAND
NOP
WRITE A
READ B
NOP
tCK1, I/O’s
CAS latency = 1
DIN A0
tCK2, I/O’s
CAS latency = 2
DIN A0
tCK3, I/O’s
CAS latency = 3
DIN A0
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Input data for the Write is ignored.
Input data must be removed from the I/O’s at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B3
don’t care
COMMAND
NOP
WRITE A
Auto-Precharge
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
BANK A
ACTIVE
NOP
DIN A0
DIN A1
DIN A0
DIN A1
*
I/O’s
CAS latency = 2
I/O’s
CAS latency = 3
Begin Autoprecharge
Bank can be reactivated after tRP
*
tDPL
tRP
DIN A0
DIN A1
tDPL
tRP
NOP
*
I/O’s
CAS latency = 1
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