參數(shù)資料
型號(hào)： V54C316162VAT10
廠(chǎng)商： MOSEL-VITELIC
元件分類(lèi)： DRAM
英文描述： 1M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO50
封裝： 0.400 INCH, PLASTIC, TSOP2-50
文件頁(yè)數(shù)： 34/61頁(yè)
文件大?。?/td> 916K
代理商： V54C316162VAT10
4
V54C316162VA Rev. 1.0 January 1998
MOSEL VITELIC
V54C316162VA
Signal Pin Description
Pin
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
inititiates either the Power Down mode, Suspend mode or the Self Refresh mode.
CS
Input
Pulse
Active Low
CS enables the command decoder when low and disables the command decoder
when high. When the command decoder is disabled, new commands are ignored but
previous operations continue.
RAS, CAS
WE
Input
Pulse
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0–A10
Input
Level
—
During a Bank Activate command cycle, A0-A10 defines the row address (RA0-RA10)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address
(CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM
organization.
1M x 16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke autoprecharge operation at
the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
A11 defines the bank to be precharged (low=bank A, high=bank B). If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with A11 to control
which bank(s) to precharge. If A10 is high, both bank A and bank B will be precharged
regardless of the state of A11. If A10 is low, then A11 is used to define which bank to
precharge.
A11 (BS)
Input
Level
—
Selects which bank is to be active. A11 low selects bank A and A11 high selects bank
B.
I/O1–I/O16
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQM
LDQM
UDQM
Input
Pulse
Active High The Data Input/Output mask places the I/O buffers in a high impedance state when
sampled high. In Read mode, DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM has a latency of zero and
operates as a word mask by allowing input data to be written if it is low but blocks the
write operation if DQM is high.
VCC, VSS
Supply
Power and ground for the input buffers and the core logic.
VCCQ, VSSQ
Supply
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
相關(guān)PDF資料
PDF描述
V54C3256164VAT6 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
V54C3256404VDS8IPC 64M X 4 SYNCHRONOUS DRAM, 6 ns, PBGA60
V54C3256404VDUG7 64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
V54C3256404VDLJ6 64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PBGA60
V54C3256404VDUI6 64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
V54C316162VC 制造商:MOSEL 制造商全稱(chēng):MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-5 制造商:MOSEL 制造商全稱(chēng):MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-55 制造商:MOSEL 制造商全稱(chēng):MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-6 制造商:MOSEL 制造商全稱(chēng):MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-7 制造商:MOSEL 制造商全稱(chēng):MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*