參數(shù)資料
型號(hào)： UPD72042
廠商： NEC Corp.
英文描述： LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
中文描述： LSI器件間設(shè)備BusTM（IEBusTM）協(xié)議控制
文件頁(yè)數(shù)： 44/92頁(yè)
文件大?。?/td> 373K
代理商： UPD72042
μ
PD72042
44
Data Sheet S14870EJ1V0DS00
DAR1
DAR2
Address
: 0110B (6H) (DAR1) High-order 4 bits
0111B (7H) (DAR2)
: Read
When reset : Undefined
Read/write
Broadcast address register
The DAR1 and DAR2 registers are used to hold a broadcast address (master address) involved when a broadcast
reception error occurs.
DAR1 and DAR2 are updated each time a broadcast reception error occurs (SLRC of the RCR register is set to
1100). So, ensure that when a broadcast reception error occurs, the contents of DAR1 and DAR2 are read by the
microcomputer within the time indicated below.
Maximum allowable DAR1 and DAR2 read time:
Approx. 5420
μ
s (mode 0)
Approx. 1490
μ
s (mode 1)
Cautions 1. If the microcomputer cannot read the data in DAR1 and DAR2 within the times indicated above,
DAR1 and DAR2 may be updated by the occurrence of another broadcast reception error, and
the subsequently updated broadcast address may be read.
2. A broadcast address is stored in DAR1 and DAR2 when DERC (broadcast reception selection)
of the CMR register is set to 1.
b7
Broadcast address (low-order 4 bits)
b4
b3
b0
—
DAR1
b7
b0
Broadcast address (high-order 8 bits)
DAR2
t
IRQ
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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