參數(shù)資料
型號(hào)： UPD44165094AF5-E40Y-EQ2
元件分類(lèi)： SRAM
英文描述： 2M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, PLASTIC, BGA-165
文件頁(yè)數(shù)： 9/40頁(yè)
文件大?。?/td> 388K
代理商： UPD44165094AF5-E40Y-EQ2
17
Data Sheet
M17771EJ3V0DS
μPD44165084A, 44165094A, 44165184A, 44165364A
Bus Cycle State Diagram
READ DOUBLE;
R_Count = R_Count+2
WRITE DOUBLE;
W_Count = W_Count+2
Power UP
Always
R# = HIGH
Supply voltage
provided
LOAD NEW
READ ADDRESS;
R_Count = 0;
R_Init = 1
READ PORT NOP
R_Init = 0
R# = LOW & R_Count = 4
W# = HIGH
WRITE PORT NOP
LOAD NEW
WRITE ADDRESS;
W_Count = 0
Always
W# = LOW & W_Count = 4
W# = LOW
R_Init = 0
R# = LOW
Supply voltage
provided
INCREMENT READ
ADDRESS BY TWO
R_Init = 0
INCREMENT WRITE
ADDRESS BY TWO
W_Count = 2
R_Count = 2
Always
W# = HIGH
& W_Count = 4
R# = HIGH
& R_Count = 4
Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
2. Read and write state machines can be active simultaneously.
Read and write cannot be simultaneously initiated. Read takes precedence.
3. State machine control timing is controlled by K.
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