參數(shù)資料
型號(hào)： UPD44165094AF5-E40Y-EQ2
元件分類(lèi)： SRAM
英文描述： 2M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, PLASTIC, BGA-165
文件頁(yè)數(shù)： 25/40頁(yè)
文件大?。?/td> 388K
代理商： UPD44165094AF5-E40Y-EQ2
31
Data Sheet
M17771EJ3V0DS
μPD44165084A, 44165094A, 44165184A, 44165364A
Output Pin States of CQ, CQ# and Q
Instructions
Control-Register Status
Output Pin Status
CQ, CQ#
Q
EXTEST
0
Update
High-Z
1
Update
IDCODE
0
SRAM
1
SRAM
SAMPLE-Z
0
High-Z
1
High-Z
SAMPLE
0
SRAM
1
SRAM
BYPASS
0
SRAM
1
SRAM
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 48).
There are three statuses:
Update : Contents of the “Update Register” are output to
the output pin (QDR Pad).
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (QDR Pad).
High-Z : The output pin (QDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
SRAM
CAPTURE
Register
Boundary Scan
Register
Update
Register
QDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
High-Z
Update
SRAM
Output
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