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參數(shù)資料
| 型號： | UPD44165094AF5-E40Y-EQ2 |
| 元件分類： | SRAM |
| 英文描述： | 2M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, PLASTIC, BGA-165 |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 388K |
| 代理商： | UPD44165094AF5-E40Y-EQ2 |
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32
Data Sheet
M17771EJ3V0DS
μPD44165084A, 44165094A, 44165184A, 44165364A
Boundary Scan Register Status of Output Pins CQ, CQ# and Q
Instructions
SRAM Status
Boundary Scan Register Status
Note
CQ, CQ#
Q
EXTEST
READ (Low-Z)
Pad
NOP (High-Z)
Pad
IDCODE
READ (Low-Z)
–
No definition
NOP (High-Z)
–
SAMPLE-Z
READ (Low-Z)
Pad
NOP (High-Z)
Pad
SAMPLE
READ (Low-Z)
Internal
NOP (High-Z)
Internal
Pad
BYPASS
READ (Low-Z)
–
No definition
NOP (High-Z)
–
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
There are two statuses:
Pad
: Contents of the output pin (QDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
Pad
Internal
SRAM
Output
Driver
Update
Register
QDR
Pad
High-Z
JTAG ctrl
CAPTURE
Register
SRAM
Output
Boundary Scan
Register
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| UPD44165094BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 2M x 9-Bit 0.45ns 165-Pin BGA |
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| UPD44324182BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:RENUPD44324182BF5-E40-FQ1-A 36M-BIT(2M-W |
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