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參數(shù)資料
| 型號： | UPD44165094AF5-E40Y-EQ2 |
| 元件分類： | SRAM |
| 英文描述： | 2M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, PLASTIC, BGA-165 |
| 文件頁數(shù)： | 40/40頁 |
| 文件大小： | 388K |
| 代理商： | UPD44165094AF5-E40Y-EQ2 |
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9
Data Sheet
M17771EJ3V0DS
μPD44165084A, 44165094A, 44165184A, 44165364A
(2/2)
Symbol
Description
CQ, CQ#
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q
tristates. If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also
stop.
ZQ
Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. The output impedance can be minimized by directly connect ZQ to VDDQ. This pin cannot be connected
directly to GND or left unconnected. The output impedance is adjusted every 1,024 cycles upon power-up to
account for drifts in supply voltage and temperature. After replacement for a resistor, the new output impedance
is reset by implementing power-on sequence.
DLL#
DLL/PLL Disable: When debugging the system or board, the operation can be performed at a clock frequency
slower than TKHKH (MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. The AC/DC characteristics
cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to VDDQ through a
10 k
Ω or less resistor.
TMS
TDI
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not
used in the circuit.
TCK
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
TDO
IEEE 1149.1 Test Output: 1.8 V I/O level.
VREF
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
VDD
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for
range.
VDDQ
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See Recommended DC
Operating Conditions and DC Characteristics for range.
VSS
Power Supply: Ground
NC
No Connect: These signals are not connected internally.
<R>
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|---|---|
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| UPD44165362BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin BGA |
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