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| 型號： | TRK-MPC5634M |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 96/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | TRAK 5634M 144PN R2.1 |
| 設(shè)計資源： | TRK-MPC5634M Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC56xx |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | MPC5634M |
| 所含物品： | 板，線纜，CD，DVD |
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Electrical characteristics
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
75
8 VFLASH is only available in the calibration package.
9 Regulator is functional, with derated performance, with supply voltage down to 4.0 V.
10 Multi-voltage pads (type pad_multv_hv) must be supplied with a power supply between 4.75 V and 5.25 V.
11 The slew rate (SRC) setting must be 0b11 when in low-swing mode.
12 While in low-swing mode there are no restrictions in transitioning to high-swing mode.
13 Pin in low-swing mode can accept a 5 V input.
14 Values are pending characterization.
15 Pin in low-swing mode can accept a 5 V input.
16 Characterization based capability:
IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH=4.5 V;
IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH=3.0 V
17 Characterization based capability:
IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE=3.0 V;
IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE=2.25 V;
IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE=1.62 V
18 All VOL/VOH values 100% tested with ± 2 mA load.
19 Run mode as follows:
System clock = 40/60/80 MHz + FM 2%
Code executed from flash memory
ADC0 at 16 MHz with DMA enabled
ADC1 at 8 MHz
eMIOS pads toggle in PWM mode with a rate between 100 kHz and 500 kHz
eTPU pads toggle in PWM mode with a rate between 10 kHz and 500 kHz
CAN configured for a bit rate of 500 kHz
DSPI configured in master mode with a bit rate of 2 MHz
eSCI transmission configured with a bit rate of 100 kHz
20 Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive
code, 4 x ADC conversion every 10 ms, 2 × PWM channels at 1 kHz, all other modules stopped.
Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules
stopped.
22 When using the internal regulator only, a bypass capacitor should be connected to this pin. External circuits should
not be powered by the internal regulator. The internal regulator can be used as a reference for an external debugger.
23 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a
particular I/O segment, and the voltage of the I/O segment. See Table 23 for values to calculate power dissipation for
specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions
for each pin on the segment.
24 Absolute value of current, measured at VIL and VIH.
25 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: fast (pad_fc).
26 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half
for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
27 Applies to CLKOUT, external bus pins, and Nexus pins.
28 Applies to the FCK, SDI, SDO, and SDS pins.
29 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor
diagnostics.
30 When the pull-up and pull-down of the same nominal 200 K or 100 K value are both enabled, assuming no
interference from external devices, the resulting pad voltage will be 0.5*VDDE ±2.5%
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