參數(shù)資料
型號： TRK-MPC5634M
廠商： Freescale Semiconductor
文件頁數(shù)： 41/122頁
文件大?。?/td> 0K
描述： TRAK 5634M 144PN R2.1
設計資源： TRK-MPC5634M Schematic
標準包裝： 1
系列： MPC56xx
類型： MCU
適用于相關產品： MPC5634M
所含物品： 板，線纜，CD，DVD
Overview
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
25
— Auxiliary Output port
– 1 MCKO (message clock out) pin
– 4 MDO (message data out) pins
–2 MSEO (message start/end out) pins
–1 EVTO (event out) pin
— Auxiliary input port
– 1 EVTI (event in) pin
17-pin Full Port interface in calibration package used on VertiCal boards
— 3.3 V interface
— Auxiliary Output port
– 1 MCKO (message clock out) pin
– 4 (reduced port mode) or 12 (full port mode) MDO (message data out) pins; 8 extra full port pins shared with
calibration bus
–2 MSEO (message start/end out) pins
–1 EVTO (event out) pin
— Auxiliary input port
– 1 EVTI (event in) pin
Host processor (e200) development support features
— IEEE-ISTO 5001-2003 standard class 2 compliant
— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities
(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires
between the discontinuities. Thus, static code may be traced.
— Watchpoint trigger enable of program trace messaging
— Data Value Breakpoints (JTAG feature of the e200z335 core): allows CPU to be halted when the CPU writes a
specific value to a memory location
– 4 data value breakpoints
–CPU only
– Detects ‘equal’ and ‘not equal’
– Byte, half word, word (naturally aligned)
NOTE
This feature is imprecise due to CPU pipelining.
— Subset of Power Architecture software debug facilities with OnCE block (Nexus class 1 features)
eTPU development support features
— IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU
— Nexus based breakpoint configuration and single step support (JTAG feature of the eTPU)
Run-time access to the on-chip memory map via the Nexus read/write access protocol. This feature supports accesses
for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid
prototyping for powertrain automotive development systems.
All features are independently configurable and controllable via the IEEE 1149.1 I/O port
Power-on-reset status indication during reset via MDO[0] in disabled and reset modes
2.2.20.2
JTAG
The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent
to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001
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