參數(shù)資料
型號(hào)： TRK-MPC5634M
廠商： Freescale Semiconductor
文件頁數(shù)： 118/122頁
文件大?。?/td> 0K
描述： TRAK 5634M 144PN R2.1
設(shè)計(jì)資源： TRK-MPC5634M Schematic
標(biāo)準(zhǔn)包裝： 1
系列： MPC56xx
類型： MCU
適用于相關(guān)產(chǎn)品： MPC5634M
所含物品： 板，線纜，CD，DVD
Electrical characteristics
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
95
4.16.3
Calibration bus interface timing
Table 38. Calibration bus operation timing 1
1 Calibration bus timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDE = 1.62 V to 3.6 V (unless stated
otherwise), TA = TL to TH, and CL = 30 pF with DSC = 0b10.
#
Symbol
C
Characteristic
66 MHz (ext. bus)2
2 The external bus is limited to half the speed of the internal bus. The maximum external bus frequency is 66 MHz.
Unit
Notes
Min
Max
1TC
CC
P CLKOUT Period
15.2
—
ns
Signals are
measured at 50%
VDDE.
2tCDC CC D CLKOUT duty cycle
45%
55%
TC
3tCRT CC D CLKOUT rise time
—
3
3 Refer to Fast Pad timing in Table 34 and Table 35 (different values for 3.3 V vs. 1.8 V).
ns
4tCFT CC D CLKOUT fall time
—
ns
5tCOH CC D CLKOUT Posedge to Output Signal
Invalid or High Z(Hold Time)
ADDR[8:31]
CS[0:3]
DATA[0:31]
OE
RD_WR
TS
WE[0:3]/BE[0:3]
1.04/1.5
4 The EBTS=0 timings are only valid/ tested at VDDE=2.25–3.6 V, whereas EBTS=1 timings are valid/tested at
1.6–3.6 V.
—
ns
Hold time selectable
via
SIU_ECCR[EBTS]
bit:
EBTS=0: 1.0ns
EBTS=1: 1.5ns
6tCOV CC D CLKOUT Posedge to Output Signal Valid
(Output Delay)
ADDR[8:31]
CS[0:3]
DATA[0:31]
OE
RD_WR
TS
WE[0:3]/BE[0:3]
—6.04/7.0
ns
Output valid time
selectable via
SIU_ECCR[EBTS]
bit:
EBTS=0: 5.5ns
EBTS=1: 6.5ns
7tCIS
CC
D Input Signal Valid to CLKOUT Posedge
(Setup Time)
DATA[0:31]
5.0
—
ns
8tCIH
CC
D CLKOUT Posedge to Input Signal Invalid
(Hold Time)
DATA[0:31]
1.0
—
ns
9tAPW CC D ALE Pulse Width5
5 Measured at 50% of ALE.
6.5
—
ns
10
tAAI
CC
D ALE Negated to Address Invalid5
3—
ns
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