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參數(shù)資料
| 型號(hào)： | TRC101 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | highly integrated single chip |
| 中文描述： | 高度集成的單芯片 |
| 文件頁數(shù)： | 27/33頁 |
| 文件大?。?/td> | 512K |
| 代理商： | TRC101 |
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27
Duty Cycle Set Register
[POR=C80Eh]
Bit
Bit
Bit
Bit
15
14
13
12
1
1
0
0
The duty cycle register may be used in conjunction with the wake-up timer to reduce the average current
consumption of the receiver. The duty cycle register may be set up so that when the wake-up timer
brings the chip out of sleep mode the receiver is turned on for a short time to sample if a signal is present
and then goes back into sleep and the process starts over.
The duty cycle uses the Multiplier value of the wake-up timer in part for its calculation. To calculate the
duty cycle use:
Duty Cycle = ((D[6..0] * 2 )+ 1)/M * 100
where M is M[7..0] of the
Wake-up Timer Period Register
.
Bit [15..8] – Command Code
: These bits are the command code that is sent serially to the processor
that identifies the bits to be written to the
Wake-up Timer Period Register
.
Bit [7..1] – Duty Cycle Multiplier
: These bits are the decimal value used to calculate the Duty Cycle or
“On time” of the Receiver after the wake-up timer has brought the TRC101 out of sleep mode.
Bit [0] – Duty Cycle Mode Enable
: This bit enables the duty cycle mode when set.
NOTE:
The receiver must be disabled (RXEN = ‘0’ in Power
Management Register
) and the wake-up
timer must be enabled (WKUPEN = ‘1’ in
Power Management Register
) for operation in this mode.
Bit
11
1
Bit
10
0
Bit
9
0
Bit
8
0
Bit
7
DC6
Bit
6
DC5
Bit
5
DC4
Bit
4
DC3
Bit
3
DC2 DC1 DC0
Bit
2
Bit
1
Bit
0
DCEN
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