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參數(shù)資料
| 型號： | TRC101 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | highly integrated single chip |
| 中文描述： | 高度集成的單芯片 |
| 文件頁數(shù)： | 7/33頁 |
| 文件大?。?/td> | 512K |
| 代理商： | TRC101 |
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7
3. TRC101 Functional Characteristics
Figure 2. Functional Block Diagram
Input/Output Amplifier
The output power amplifier is an open-collector, differential output with programmable output power which
can directly drive a loop or dipole antenna, and with proper matching may also drive a monopole antenna.
Incorporated in the power amplifier is an automatic antenna tuning circuit to avoid manual tuning during
production and to offset “hand effects”. Registers common to the Power Amplifier are:
Power Management Register
Transmit Configuration Register
The input LNA has selectable gain (0dB, -6dB, -14dB, -20dB) which may be useful in an environment with
strong interferers. The LNA has a 250
Ohm differential input impedance which requires a matching
circuit when connected to 50 Ohm devices. Registers common to the LNA are:
Power Management Register
Receiver Control Register
Baseband Data and Filtering
The baseband receiver has several programmable options that optimize the data link for a wide range of
applications. The programmable functions include:
Receive bandwidth
Receive data rate
Baseband Analog Filter
Baseband Digital Filter
Clock Recovery (CR)
Receive FIFO
Data Quality Detector
Valid Data Detector
The receive bandwidth is programmable from 67kHz to 400kHz to accommodate various FSK modulation
deviations. If the deviation is known for a given transmitter, the best results are obtained with a
bandwidth at least twice the transmitter FSK deviation.
PA
LNA
VCO
PLL
/N
T X/RX
OSC
0/90
+
-
I/Q
DEMOD
ASK
F SK
CONT ROL
LOGIC
BAT T DET
SDO
SCK
nCS
SDI
nIRQ
DAT A / nF SEL
CR/F INT /F CAP
CLKOUT
XT AL/REF
VDD
nRESET
GND
RSSIA
nINT /DDET
RSSI
R
RF _P
RF _N
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