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參數(shù)資料
| 型號(hào)： | TRC101 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | highly integrated single chip |
| 中文描述： | 高度集成的單芯片 |
| 文件頁(yè)數(shù)： | 19/33頁(yè) |
| 文件大?。?/td> | 512K |
| 代理商： | TRC101 |
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19
Receiver Control Register
[POR=9080h]
Bit Bit Bit Bit Bit
15 14 13 12 11
1
0
0
1
0
INT/VDI VDIR1 VDIR0
The Receiver Control Register configures the following:
Receiver LNA gain
Digital RSSI threshold
Receive baseband bandwidth
Valid Data Detector response time
Function of pin 16
Bit [15..11] – Command Code
: These bits are the command code that is sent serially to the processor
that identifies the bits to be written to the Receiver Control Register.
Bit [10] – Pin 16 Func
: Selects the function of Pin 16. See Table 10 below.
Bit
10
Bit
9
Bit
8
Bit
7
BB2
Bit
6
BB1
Bit
5
BB0
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
GAIN1
GAIN0 RSSI2 RSSI1
RSSI0
Table 10.
Pin 16 Function
Interrupt Input
Valid Data Output
INT/VDI
0
1
Bit [9..8] – Valid Data Detector Response Time
: When Pin 16 is selected as Valid Data Detector output
these bits set the response time in which the TRC101 will detect the incoming synchronous bit pattern
and issue an interrupt to the host processor. See Table 11 below for response settings.
Table 11.
VDI Response Time
Fast
Mid
Slow
Continuous
VDIR1
0
0
1
1
VDIR0
0
1
0
1
Figure 4. VDI Signal Response Configuration
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