- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385015 > TRC101 (RF Monolithics, Inc.) highly integrated single chip PDF資料下載
參數(shù)資料
| 型號(hào)： | TRC101 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | highly integrated single chip |
| 中文描述： | 高度集成的單芯片 |
| 文件頁數(shù)： | 12/33頁 |
| 文件大?。?/td> | 512K |
| 代理商： | TRC101 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
12
4.
Control and Configuration Registers
Status Register
(Read Only)
Bit
Bit
Bit
14
13
12
Bit
15
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
FIFTXRX
POR
FIFOV/UR
WKINT
INTRST
LB
FIFEMP
RSSI/AT
GDQD
CRLCK
AFATGL
OFFSGN
OFF3
OFF2
OFF1
OFF0
The Status Register provides feedback for:
FIFO ready/full/empty/under run/overwrite
POR
Interrupt state
Low Battery
Good Data Quality
Digital RSSI signal level
Clock Recovery
Frequency Offset value and sign
AFA
Note: The Status Register read command begins with a logic ‘0’ where all other register commands begin
with a logic ‘1’.
Bit [15]:FIFTXRX
– When set, indicates the transmit register is ready to receive the next byte for
transmission (Transmit Mode) or that the Rx FIFO has reached the
preprogrammed limit (Receive Mode). This bit is multiplexed and dependent on
whether you are in the respective Transmit or Receive mode. (Cleared when FIFO
read).
Bit [14]:POR
– When set, Power-on Reset occurred. (Cleared after Status Reg read).
Bit [13]:FIFOV/UR
– When set, indicates transmit register under run or register overwrite (Transmit
Mode) or receive FIFO overflow (Receive Mode). (Cleared after Status Reg read).
Bit [12]:WKINT
– When set, indicates a Wake-up timer overflow. (Cleared after Status Reg read).
Bit [11]:INTRST
– When set, indicates a High to Low logic level change on interrupt pin (pin 16).
(Cleared after Status Reg read).
Bit [10]:LB
– When set, indicates the supply voltage is below the preprogrammed limit. See Battery
Detect Threshold and Clock Output Register.
Bit [9]:FIFEMP
– When set, indicates receive FIFO is empty.
Bit [8]:RSSI(Rx)
– When set and chip in receive mode, this bit indicates that the incoming RF signal is
above the preprogrammed Digital RSSI limit.
AT(TX
) – When in transmit mode this bit indicates that the antenna tuning circuit has detected a
strong enough RF signal.
Bit [7]:GDQD
– When set, indicates good data quality.
Bit [6]:CRLCK
– When set, indicates Clock Recovery is locked.
Bit [5]:AFATGL
– For each AFC cycle run, this bit will toggle between logic ‘1’ and logic ‘0’.
Bit [4]:OFFSGN
– Indicates the difference in frequency is higher (logic ‘1’) or lower (logic ‘0’) than the
chip frequency.
Bit [3..0]:OFF[3..0]
– The offset value to be added to the frequency control word (internal PLL).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TRC102 | 400-1000MHz RF Transceiver |
| TRF2052 | LOW-VOLTAGE 2-GHz SYNTHESIZER |
| TRF2052PW | LOW-VOLTAGE 2-GHz SYNTHESIZER |
| TRF2432_07 | Dual-Band IQ/IF TRANSCEIVER WITH DUAL VCO SYNTHESIZERS |
| TriCore | 32-bit microcontrollers(32位微控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TRC10-103 | 制造商:RCD 制造商全稱:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM |
| TRC10-104 | 制造商:RCD 制造商全稱:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM |
| TRC10-105 | 制造商:RCD 制造商全稱:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM |
| TRC10-106 | 制造商:RCD 制造商全稱:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM |
| TRC10-107 | 制造商:RCD 制造商全稱:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。