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參數(shù)資料
| 型號： | TRC101 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | highly integrated single chip |
| 中文描述： | 高度集成的單芯片 |
| 文件頁數(shù)： | 22/33頁 |
| 文件大小： | 512K |
| 代理商： | TRC101 |
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22
FIFO Read Register
[POR=B000h]
Bit
Bit
Bit
Bit
15
14
13
12
1
0
1
1
The FIFO Read Register stores the received data and can be read out by the host processor. The FIFO
must be enabled by setting Bit[6] of the
Configuration Register
.
Bit [15..8] - Command Code
: These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the
Data FIFO Configuration Register
.
Bit [7..0] – FIFO Data Bits
: These bits are the recovered data bits stored in the FIFO. These bits may be
read out over the SPI bus.
Bit
11
0
Bit
10
0
Bit
9
0
Bit
8
0
Bit
7
RX7
Bit
6
RX6
Bit
5
RX5
Bit
4
RX4
Bit
3
RX3
Bit
2
RX2
Bit
1
RX1
Bit
0
RX0
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