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SPRS457E
– MARCH 2009 – REVISED JUNE 2011
6.21 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the
network. The EMAC supports both 10Base-T (10 Mbits/second [Mbps]) and 100Base-TX (100 Mbps) in
either half- or full-duplex mode. The EMAC module also supports hardware flow control and quality of
service (QOS) support.
The frequencies supported for transmit and receive clocks are fixed by the IEEE 802.3 standard as:
2.5 MHz for 10Mbps
25 MHz for 100Mbps
The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY
configuration and status monitoring.
The EMAC module conforms to the IEEE 802.3-2002 standard, describing the
“Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer
” specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER.
Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will
intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame
will be detected as an error by the network
Both the EMAC and the MDIO modules interface to the device through a custom interface that allows
efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
For more information on the TMS320DM36x DMSoC Ethernet Media Access Controller User's Guide
6.21.1 EMAC Peripheral Register Description(s)
Table 6-89 lists the EMAC registers, their corresponding acronyms, and the device memory locations
(offsets).
Table 6-89. Ethernet Media Access Controller (EMAC) Control Module Registers
Slave VBUS
Acronym
Register Description
Address Offset
0h
CMIDVER
Identification and Version Register
04h
CMSOFTRESET
Software Reset Register
08h
CMEMCONTROL
Emulation Control Register
Ch
CMINTCTRL
Interrupt Control Register
10h
CMRXTHRESHINTEN
Receive Threshold Interrupt Enable Register
14h
CMRXINTEN
Receive Interrupt Enable Register
18h
CMTXINTEN
Transmit Interrupt Enable Register
1Ch
CMMISCINTEN
Miscellaneous Interrupt Enable Register
40h
CMRXTHRESHINTSTAT
Receive Threshold Interrupt Status Register
44h
CMRXINTSTAT
Receive Interrupt Status Register
48h
CMTXINTSTAT
Transmit Interrupt Status Register
4Ch
CMMISCINTSTAT
Miscellaneous Interrupt Status Register
70Ch
CMRXINTMAX
Receive Interrupts Per Millisecond Register
74h
CMTXINTMAX
Transmit Interrupts Per Millisecond Register
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2009–2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
187