![](http://datasheet.mmic.net.cn/Texas-Instruments/TMX320DM365BZCE_datasheet_99828/TMX320DM365BZCE_151.png)
SPRS457E
– MARCH 2009 – REVISED JUNE 2011
Table 6-56. Universal Serial Bus (USB) Registers (continued)
Offset
Acronym
Register Description
1A0h
RCPPIDMASTATEW0
Receive CPPI DMA State Word 0
1A4h
RCPPIDMASTATEW1
Receive CPPI DMA State Word 1
1A8h
RCPPIDMASTATEW2
Receive CPPI DMA State Word 2
1ACh
RCPPIDMASTATEW3
Receive CPPI DMA State Word 3
1B0h
RCPPIDMASTATEW4
Receive CPPI DMA State Word 4
1B4h
RCPPIDMASTATEW5
Receive CPPI DMA State Word 5
1B8h
RCPPIDMASTATEW6
Receive CPPI DMA State Word 6
1BCh
RCPPICOMPPTR
Receive CPPI Completion Pointer
Transmit/Receive CPPI Channel 3 State Block
1C0h
TCPPIDMASTATEW0
Transmit CPPI DMA State Word 0
1C4h
TCPPIDMASTATEW1
Transmit CPPI DMA State Word 1
1C8h
TCPPIDMASTATEW2
Transmit CPPI DMA State Word 2
1CCh
TCPPIDMASTATEW3
Transmit CPPI DMA State Word 3
1D0h
TCPPIDMASTATEW4
Transmit CPPI DMA State Word 4
1D4h
TCPPIDMASTATEW5
Transmit CPPI DMA State Word 5
1DCh
TCPPICOMPPTR
Transmit CPPI Completion Pointer
1E0h
RCPPIDMASTATEW0
Receive CPPI DMA State Word 0
1E4h
RCPPIDMASTATEW1
Receive CPPI DMA State Word 1
1E8h
RCPPIDMASTATEW2
Receive CPPI DMA State Word 2
1ECh
RCPPIDMASTATEW3
Receive CPPI DMA State Word 3
1F0h
RCPPIDMASTATEW4
Receive CPPI DMA State Word 4
1F4h
RCPPIDMASTATEW5
Receive CPPI DMA State Word 5
1F8h
RCPPIDMASTATEW6
Receive CPPI DMA State Word 6
1FCh
RCPPICOMPPTR
Receive CPPI Completion Pointer
Common USB Registers
400h
FADDR
Function Address Register
401h
POWER
Power Management Register
402h
INTRTX
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
404h
INTRRX
Interrupt Register for Receive Endpoints 1 to 4
406h
INTRTXE
Interrupt enable register for INTRTX
408h
INTRRXE
Interrupt Enable Register for INTRRX
40Ah
INTRUSB
Interrupt Register for Common USB Interrupts
40Bh
INTRUSBE
Interrupt Enable Register for INTRUSB
40Ch
FRAME
Frame Number Register
40Eh
INDEX
Index Register for Selecting the Endpoint Status and Control Registers
40Fh
TESTMODE
Register to Enable the USB 2.0 Test Modes
Indexed Registers
These registers operate on the endpoint selected by the INDEX register
410h
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint.
(Index register set to select Endpoints 1-4)
412h
PERI_CSR0
Control Status Register for Endpoint 0 in Peripheral Mode.
(Index register set to select Endpoint 0)
HOST_CSR0
Control Status Register for Endpoint 0 in Host Mode.
(Index register set to select Endpoint 0)
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint.
(Index register set to select Endpoints 1-4)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint.
(Index register set to select Endpoints 1-4)
Copyright
2009–2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
151