![](http://datasheet.mmic.net.cn/Texas-Instruments/TMX320DM365BZCE_datasheet_99828/TMX320DM365BZCE_51.png)
SPRS457E
– MARCH 2009 – REVISED JUNE 2011
3.2
Boot Modes
The ARM can boot from either Asynchronous EMIF (OneNand/NOR) or from ARM ROM, as determined
by the setting of the device configuration pins BTSEL[2:0]. The boot selection pins (BTSEL[2:0]) determine
the ARM boot process. After reset (POR, warm reset, or max reset), ARM program execution begins in
ARM ROM at 0x0000: 8000, except when BTSEL[2:0] = 001, indicating AEMIF (OneNand/NOR) flash
boot.
3.2.1
Boot Modes Overview
The ARM ROM boot loader (RBL) executes when the BTSEL[2:0] pins indicate a condition other than the
normal ARM EMIF boot.
If BTSEL[2:0] = 001 - Asynchronous EMIF boot mode (NOR or OneNAND). This mode is handled by
hardware control and does not involve the ROM. In the case of OneNAND, the user is responsible for
putting any necessary boot code in the OneNAND's boot page. This code shall configure the AEMIF
module for the OneNAND device. After the AEMIF module is configured, booting will continue
immediately after the OneNAND
’s boot page with the AEMIF module managing pages thereafter.
The RBL supports 7 distinct boot modes:
– BTSEL[2:0] = 000 - NAND Boot mode
– BTSEL[2:0] = 010 - MMC0/SD0 Boot mode
– BTSEL[2:0] = 011 - UART0 Boot mode
– BTSEL[2:0] = 100 - USB Boot mode
– BTSEL[2:0] = 101 - SPI0 Boot mode
– BTSEL[2:0] = 110 - EMAC Boot mode
– BTSEL[2:0] = 111 - HPI Boot mode
If NAND boot fails, then MMC/SD mode is tried.
If MMC/SD boot fails, then MMC/SD boot is tried again.
If UART boot fails, then UART boot is tried again.
If USB boot fails, then USB boot is tried again.
If SPI boot fails, then SPI boot is tried again.
If EMAC boot fails, then EMAC boot is tried again.
If HPI boot fails, then HPI boot is tried again.
RBL shall update boot status (PASS/FAIL) in MISC register bits 8 and 9 in System control module.
ARM ROM Boot - NAND Mode
– No support for a full firmware boot. Instead, copies a second stage user boot loader (UBL) from
NAND flash to ARM internal RAM (AIM) and transfers control to the user-defined UBL.
– Support for NAND with page sizes up to 4096 bytes.
– Support for magic number error detection and retry (up to 24 times) when loading UBL
– Support for up to 30KB UBL (32KB IRAM - ~2KB for RBL stack)
– Optional, user-selectable, support for use of DMA and I-cache during RBL execution (i.e.,while
loading UBL)
– Supports booting from 8-bit NAND devices (16-bit NAND devices are not supported)
– Uses/Requires 4-bit HW ECC (NAND devices with ECC requirements ≤ 4 bits per 512 bytes are
supported)
– Supports NAND flash that requires chip select to stay low during the tR read time
Copyright
2009–2011, Texas Instruments Incorporated
Device Configurations
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