
SPRS457E
– MARCH 2009 – REVISED JUNE 2011
3.3.6
PLL Controller Clocking Configurations Examples
The DM365 uses two PLLs to generate the two fundamental clocks used on the device. These two clocks
feed two divider blocks which generate all of the functional clocks used by the peripherals and cores in the
DM365. There are some peripheral clocks on the DM365 which are required to operate at a specific
frequency by functional specification or convention. These frequencies are detailed in
Table 3-5.Table 3-5. Specific Peripheral Operating Frequencies
Clock
Required Frequency (MHz)
Reason
VENC (standard definition)
27
required to generate a valid NTSC signal
VENC (high definition)
74.25
required to generate a valid ATSC signal
USB
36, 24, or 19.2
required by the USB peripheral to generate a 48 MHz USB clock
Voice Codec
4.096
required to generate a precise 16 kHz audio sample rate
DM365. Please see the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number
SPRUFG5) for additional details on special peripherals, clocking considerations, and for additional PLL
controller configuration details.
Note 1: A 300-MHz configuration is possible using different PLL multiplier/divider combinations. However,
an external clock source is required to provide 74.25 MHz for HD display.
Note 2: HD 720p and above display mode resolutions are not supported on ARM 216-MHz clock rate
devices.
Note 3: There are example cases where the voice codec sampling frequency is listed as 15.98 kHz or
16.002 kHz. The difference of 0.125% or 0.0125% versus 16 kHz specification should be acceptable for
the majority of audio applications. If the DM365 voice codec is required to operate at precisely 16 kHz
then the functional clock can be reduced to achieve precisely that sample frequency but the ARM926 and
HDVICP will have to run at a reduced rate resulting in lower video performance.
Table 3-6. 24-MHz Input Crystal Example(1) (2)(3)
PLL1
PLL2
ARM
DDR
MJCP
HDVICP
Voice Codec
(4)
Video Encoder
PLL Output
(2M/(N+1))
PLL Output
(2M/(N+1))
27MHz
74.25MHz
(5)(MHz)
(MHz)
343.58
272/18
409.6
256/15
204.8
171.8
1/100
-
343.58
272/18
432
18/1
216
171.8
-
1/16
-
432
18/1
270
90/8
270
216
1/66 (15.98
1/10
-
kHz)
486
162/8
594
198/8
297
243
1/145 (16.002
1/22
1/8
kHz)
540
360/16
594
396/16
297
270
1/145 (16.002
1/20
1/8
kHz)
(1)
M = PLL controller multiplier. N = PLL controller divider.
(2)
All shaded frequencies derive from the PLL2 controller.
(3)
PLLC1SYSCLK4 (Configuration bus clock, peripheral system interfaces, EDMA) should be half of the PLLC1SYSCLK3 (MJCP and
HDVICP bus interface clock).
(4)
The Voice Codec divider value is the combination of the PLL controller 2 SYSCLK4 and Peripheral Clock Control Register PLLDIV2 bit
setting divider.
(5)
PLL Output is calculated by = Oscillator Input * (2M/(N+1)).
60
Device Configurations
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2009–2011, Texas Instruments Incorporated