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參數(shù)資料
| 型號： | TMS418169P-70 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| 中文描述： | 1048576字由16位擴充數(shù)據(jù)輸出高速DRAM等 |
| 文件頁數(shù)： | 53/67頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | TMS418169P-70 |
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH 1996
53
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
PARAMETER MEASUREMENT INFORMATION
tw(RH)
RAS
CASx
tsu(RA)
A0
–
A8
WE
TRG
DSF
DQ0
–
DQ15
tw(RL)P
td(RLCH)
td(RLCL)
tw(CL)
tw(CH)
tc(P)
th(RA)
th(RLCA)
tsu(CA)
th(CLCA)
td(CARH)
1
2
2
3
tsu(TRG)
th(TRG)
tsu(WMR)
th(RWM)
tsu(SFR)
th(SFR)
tsu(SFC)
tsu(WCH)
tsu(WRH)
tsu(DQR)
th(RDQ)
tsu(DCL)
th(CLD)
th(WLD)
th(RLD)
Row
Column
Column
td(CHRL)
4
5
5
th(RSF)
See Note A
td(RLCA)
td(CLRH)
th(SFC)
tsu(SFC)
th(SFC)
td(CHRL)
tsu(DWL)
tsu(WCH)
tw(WL)
td(CACH)
DQ0
–
DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. In early-write operations, tsu(DWL)
and th(WLD) are not applicable; tsu(DCL) and th(CLD) are referenced only to the first falling edge of CASx. In late-write operations, tsu(DCL) and
th(CLD) are not applicable.
NOTE A: A read cycle or a read-modify-write cycle can be mixed with write cycles as long as read- and read-modify-write timing specifications
are not violated.
Figure 44. Enhanced-Page-Mode Write-Cycle Timing
Table 12. Enhanced-Page-Mode Write-Cycle State Table
CYCLE
STATE
1
2
3
4
5
Write operation (nonmasked)
L
L
H
Don
’
t care
Valid data
Write operation with nonpersistent write-per-bit
L
L
L
Write mask
Valid data
Write operation with persistent write-per-bit
L
L
L
Don
’
t care
Valid data
Load-write-mask register on either the first falling edge of
WE or the falling edge of CASx, whichever occurs later.
H
L
H
Don
’
t care
Write mask
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