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參數(shù)資料
| 型號： | TMS418169P-70 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| 中文描述： | 1048576字由16位擴充數(shù)據(jù)輸出高速DRAM等 |
| 文件頁數(shù)： | 37/67頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | TMS418169P-70 |
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT.
’
551xx-60
MIN
35
’
551xx-70
MIN
40
UNIT
SYMBOL
MAX
MAX
t(P)
tc(P)
Cycle time page mode read write
Cycle time, page-mode read, write
’
551x0
tPC
tPC
tRC
tRMW
tPRMW
tSCC
tRC
tWC
tCPN
tCAS
tCAS
tTP
tRP
tRAS
tRASP
tSC
tSCP
ns
’
551x1
30
30
ns
tc(rd)
tc(rdW)
tc(RDWP)
tc(SC)
tc(TRD)
tc(W)
tw(CH)
Cycle time, read
110
130
ns
Cycle time, read-modify-write
150
175
ns
Cycle time, page-mode read-modify-write
80
90
ns
Cycle time, serial clock (see Note 9)
18
22
ns
Cycle time, transfer read
110
130
ns
Cycle time, write
110
130
ns
Pulse duration, CASx high
10
10
ns
t(CL)
tw(CL)
P l
Pulse duration, CASx low (see Note 10)
CAS l
N t 10)
’
551x0
10
10 000
10
10 000
ns
’
551x1
17
10 000
20
10 000
ns
tw(GH)
tw(RH)
tw(RL)
tw(RL)P
tw(SCH)
tw(SCL)
tw(TRG)
tw(WL)
tsu(CA)
tsu(DCL)
Pulse duration, TRG high
20
20
ns
Pulse duration, RAS high
40
50
ns
Pulse duration, RAS low (see Note 11)
60
10 000
70
10 000
ns
Pulse duration, RAS low (page mode)
60
100 000
70
100 000
ns
Pulse duration, SC high
5
8
ns
Pulse duration, SC low
5
8
ns
Pulse duration, TRG low
15
20
ns
Pulse duration, WE low
tWP
tASC
tDSC
10
10
ns
Setup time, column address before CASx low
0
0
ns
Setup time, data valid before CASx low, early write
0
0
ns
tsu(DQR)
Setup time, write mask valid before RAS low,
non-persistent write-per-bit
tMS
0
0
ns
tsu(DWL)
tsu(RA)
tsu(rd)
tsu(SFC)
tsu(SFR)
tsu(TRG)
tsu(WCH)
tsu(WCL)
tsu(WMR)
tsu(WRH)
th(CHrd)
th(CLCA)
th(CLD)
th(CLQ)
Timing measurements are referenced to VIL max and VIH min.
NOTES:
9. Cycle time assumes tt = 3 ns.
10. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user
’
s transition times, this can require
additional CASx low time [tw(CL)].
11. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user
’
s transition times, this can require
additional RAS low time [tw(RL)].
12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
Setup time, data valid before WE low, late write
tDSW
tASR
tRCS
tFSC
tFSR
tTHS
tCWL
tWCS
tWSR
tRWL
tRCH
tCAH
tDH
tDHC
0
0
ns
Setup time, row address before RAS low
0
0
ns
Setup time, WE high before first CASx low, read
0
0
ns
Setup time, DSF before first CASx low
0
0
ns
Setup time, DSF before RAS low
0
0
ns
Setup time, TRG before RAS low
0
0
ns
Setup time, WE low before both CASx high, write
15
15
ns
Setup time, WE low before first CASx low, early write
0
0
ns
Setup time, WE low before RAS low, write-per-bit
0
0
ns
Setup time, WE low before RAS high, write
15
15
ns
Hold time, WE high after both CASx high, read (see Note 12)
0
0
ns
Hold time, column address after first CASx low
10
10
ns
Hold time, data valid after first CASx low, early write
15
15
ns
Hold time, DQ output after CASx low (TMS551x1)
4
5
ns
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