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參數(shù)資料
| 型號： | TMS418169P-70 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| 中文描述： | 1048576字由16位擴充數(shù)據(jù)輸出高速DRAM等 |
| 文件頁數(shù)： | 27/67頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | TMS418169P-70 |
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
27
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
load color register (continued)
RAS
CASx
A0
–
A8
WE
TRG
DSF
DQ0
–
DQ15
1
2
3
5
6
Load-Mask-Register Cycle
Load-Color-Register Cycle
Persistent Write-Per-Bit
Block-Write Cycle
1
4
Legend:
1. Refresh address: A0
–
A8 are latched on the falling edge of RAS.
2. Row address: A0
–
A8 are latched on the falling edge of RAS.
3. Block address A2
–
A8 (TMS5516x) or A3
–
A8 (TMS5517x) are latched on the first falling edge of CASx.
4. Color data: DQ0
–
DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first.
5. Write-mask data: DQ0
–
DQ15 are latched on the falling edge RAS.
6. Column-mask data: DQ0
–
DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first.
= don
’
t care
Figure 18. Example of a Persistent Block Write
DRAM-to-SAM transfer operation
During the DRAM-to-SAM transfer operation, one-half of a row (256 columns) in the DRAM array is selected
to be transferred to the 256-bit serial-data register. The transfer operation is invoked by bringing TRG low and
holding WE high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of RAS,
determines whether the full-register-transfer operation or the split-register-transfer operation is performed.
Table 5. SAM Function Table
FUNCTION
RAS FALL
CASx
FALL
ADDRESS
DQ0
–
DQ15
MNEMONIC
CODE
CASx
TRG
WE
DSF
DSF
RAS
CASx
RAS
CASx
WE
Full-register-transfer read
H
L
H
L
X
Row
Addr
Row
Addr
Tap
Point
Tap
Point
X
X
RT
Split-register-transfer read
H
L
H
H
X
X
X
SRT
Logic L is selected when either or both CASL and CASU are low.
X =
don
’
t care
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