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| 型號： | TMS418169P-70 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| 中文描述： | 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等 |
| 文件頁數(shù)： | 39/67頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | TMS418169P-70 |
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
39
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
ALT.
’
551xx-60
MIN
’
551xx-70
MIN
UNIT
SYMBOL
MAX
MAX
td(GHQSF)
Delay time, TRG high to QSF switching, full-register transfer
(see Note 16)
tTQD
25
30
ns
td(GLRH)
td(GLZ)
Delay time, TRG low to RAS high
tROH
tOELZ
10
15
ns
Delay time, TRG low to DQ in the low-impedance state
3
3
ns
td(MSRL)
Delay time, last SC high at boundary (127 or 255) to RAS low,
split-register transfer
15
20
ns
td(RHCL)
Delay time, RAS high to first CASx low, CBR refresh
tRPC
0
0
ns
td(RHMS)
Delay time, RAS high to last SC high at boundary (127 or 255),
split-register-transfer
15
20
ns
td(RLCA)
Delay time, RAS low to column address valid
tRAD
tCSH
tCSH
tCHR
tRCD
15
30
15
35
ns
’
551x0
60
70
ns
td(RLCH)
Delay time, RAS low to CASx high
’
551x1
53
60
ns
CBR
10
10
ns
td(RLCL)
Delay time, RAS low to first CASx low (see Note 17)
20
43
20
50
ns
td(RLQSF)
Delay time, RAS low to QSF switching, full-register transfer
(see Note 16)
tRQD
65
70
ns
td(RLSH)
Delay time, RAS low to first SC high after TRG high,
early-load full-register transfer
tRSD
65
70
ns
td(RLTH)
td(RLWL)
Delay time, RAS low to TRG high (see Note 18)
tRTH
tRWD
50
55
ns
Delay time, RAS low to WE low, read-modify-write
80
95
ns
td(SCQSF)
Delay time, last SC high at boundary (127 or 255) to QSF switching,
split-register transfer (see Note 16)
tSQD
20
25
ns
td(SCTR)
td(THRH)
td(THRL)
td(THSC)
trf(MA)
tt
Timing measurements are referenced to VIL max and VIH min.
NOTES: 16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is
VOH / VOL = 2 V/0.8 V.
17. The maximum value is specified only to assure RAS access time.
18. Real-time-load and late-load full-register transfer
Delay time, SC high to TRG high, full-register transfer
tTSL
tTRD
tTRP
tTSD
tREF
tT
5
5
ns
Delay time, TRG high to RAS high (see Note 18)
–
10
–
10
ns
Delay time, TRG high to RAS low (see Note 18)
40
50
ns
Delay time, TRG high to SC high (see Note 18)
20
25
ns
Refresh time interval, memory
8
8
ms
Transition time
3
50
3
50
ns
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