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參數(shù)資料
| 型號： | TMS418169P-70 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| 中文描述： | 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等 |
| 文件頁數(shù)： | 29/67頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | TMS418169P-70 |
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
29
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
split-register-transfer read
In split-register-transfer operations, the serial-data register is split into halves (see Figure 21). The low half
contains bits 0
–
127, and the high half contains bits 128
–
255. While one half is being read out of the SAM port,
the other half can be loaded from the memory array.
512
×
512
Memory Array
256-Bit
Data Register
0
255 256
511
0
255
A8 = 0
A8 = 1
Figure 21. Split-Register-Transfer Read
To invoke a split-register-transfer cycle, DSF is brought high, TRG is brought low, and both are latched at the
falling edge of RAS (see Figure 22). Nine row-address bits (A0
–
A8) are also latched at the falling edge of RAS
to select one of the 512 rows available for the transfer. Eight of the nine column-address bits (A0
–
A6 and A8)
are latched at the first falling edge of CASx. Column-address bit A8 selects which half of the row is to be
transferred. Column-address bit A7 is ignored, and the split-register transfer is internally controlled to select the
inactive half. Column-address bits A0
–
A6 select one of 127 tap points in the specified half of SAM. Locations
127 and 255 are not valid tap points in split-register-transfer operations. In stop-point mode, stop-point locations
are not valid tap points in split-register-transfer operations.
Full XFER
RAS
Split XFER
Split XFER
Split XFER
A
B
0
511
A8 = 0
A
B
0
255
SQ
A
B
C
0
A7 = 0
511
A8 = 1
C
B
0
255
A
B
C
D
0
A7 = 1
511
A8 = 1
C
D
0
255
SQ
A
B
C
D
E
0 A7 = 0
511
A8 = 0
E
D
0
255
SQ
SQ
DRAM
SAM
A7 shown is internally controlled.
Figure 22. Example of a Split-Register-Transfer Read Operation
A full-register transfer must precede the first split-register transfer to ensure proper operation. After the
full-register transfer cycle, the first split-register transfer can follow immediately without any minimum SC clock
requirement.
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| TMS418169P-80 | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| TMS4500A-15NL | DRAM Controller |
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| TMS4500A-20N | DRAM Controller |
| TMS4500A-20NL | DRAM Controller |
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| TMS418169P-80 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| TMS4256 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS4256-10FM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS4256-10FME | 制造商:TI 制造商全稱:Texas Instruments 功能描述:262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
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