參數(shù)資料
型號(hào)： TMS418169P-70
廠商： Texas Instruments, Inc.
英文描述： 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
中文描述： 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等
文件頁數(shù)： 28/67頁
文件大?。?/td> 1464K
代理商： TMS418169P-70
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
28
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
full-register-transfer read
A full-register-transfer operation loads data from a selected half of a row in the DRAM into the SAM. TRG is
brought low and latched at the falling edge of RAS. Nine row-address bits (A0
–
A8) are also latched at the falling
edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits (A0
–
A8)
are latched at the first falling edge of CASx, where address bit A8 selects which half of the row is transferred.
Address bits A0
–
A7 select one of the SAM
’
s 256 available tap points from which the serial data is read out (see
Figure 19).
512
×
512
Memory Array
256-Bit
Data Register
0
255 256
511
0
255
A8 = 0
A8 = 1
Figure 19. Full-Register-Transfer Read
A full-register transfer can be performed in three ways: early load, real-time load (or midline load), or late load.
Each of these offers the flexibility of controlling the TRG trailing edge in the full-register-transfer cycle
(see Figure 20).
Early Load
Real-Time Load
Late Load
RAS
CASx
A0
–
A8
TRG
WE
Row
Tap
Point
Row
Tap
Point
Row
Tap
Point
SC
Tap
Bit
Tap
Bit
Tap
Bit
Old
Data
Old
Data
Old
Data
Old
Data
Old
Data
Figure 20. Example of Full-Register-Transfer Read Operations
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
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