參數(shù)資料
型號(hào): TMS418169P-70
廠商: Texas Instruments, Inc.
英文描述: 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
中文描述: 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等
文件頁(yè)數(shù): 18/67頁(yè)
文件大?。?/td> 1464K
代理商: TMS418169P-70
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
MARCH1996
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
persistent write-per-bit
The persistent write-per-bit mode is initiated only by performing a load-write-mask-register (LMR) cycle first.
In the persistent write-per-bit mode, the write-per-bit mask is not overwritten but remains valid over an arbitrary
number of write cycles until another LMR cycle is performed or until power is removed.
The LMR cycle is performed using DRAM write-cycle timing except DSF is held high on the falling edge of RAS
and held low on the first falling edge of CASx. A binary code is input to the write-mask register through the
random I/O pins and latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs
later. Byte-write control can be applied to the write mask during the LMR cycle. The persistent write-per-bit mode
can then be used in exactly the same way as the nonpersistent write-per-bit mode except that the input data
on the falling edge of RAS is ignored. When the device is set to the persistent write-per-bit mode, it remains in
this mode and is reset only by a CBR refresh with option reset cycle (see Figure 8).
RAS
CASx
A0
A8
DSF
Load Write-Mask Register
Persistent Write-Per-Bit
DQ0
DQ15
Write-Mask
Data
Valid
Input
CBR Refresh (option reset)
WE
Refresh
Address
Row
Column
Mask Data
=
=
1: Write to DQ enabled
0: Write to DQ disabled
Figure 8. Example of a Persistent Write-Per-Bit Operation
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